NoBL SRAMs are popular for networking and communication systems, as well as for test equipment applications. Like their standard synchronous-burst SRAM counterparts, NoBL SRAMs are available in both flow-through and pipelined SDR architectures. In burst mode, designers have a choice between linear and interleaved burst modes.
NoBL burst SRAMs have been specially designed to eliminate the bus turnaround delay associated with switching between read and write operations. These devices are also known as zero bus turnaround (ZBT) SRAM.
The NoBL architecture eliminates the wait periods between reads and writes, resulting in I/O bus utilization of close to 100%. This can dramatically improve the bandwidth in a given system.
Both standard synchronous SRAMs and NoBL SRAMs have common I/O architecture. Choice of whether to use a standard synchronous or NoBL SRAM depends on the application (see table 1). Standard synchronous SRAMs are effective for caching applications or dominated read or write conditions. NoBL SRAMs are more effective under balanced read and write conditions since they eliminate the latency between reads and writes.
Table 1: Comparison of standard synchronous SRAMs and NoBL SRAMs
Now let’s move onto the quad data rate (QDR) family of SRAM devices, which includes QDR and QDRII. QDR stands for quad data rate. QDR SRAMs are similar to NoBL SRAMs but with architectural enhancements such as double data rate I/Os and dedicated read/write ports to eliminate bus contention. QDR also has high-speed transceiver logic (HSTL) levels along with a programmable output impedance setting. QDR has separate and independent inputs and outputs. This means the user can be reading and writing from the part at the same time.
Quad data rate was given its name because at any given cycle, it can have two data words coming out of the QDR device and two data word going into the QDR device. QDR SRAMs are used in networking applications in which reads and writes are balanced, such as packet buffers, statistics counters, flow states, and scheduling. QDR SRAMs have a maximum clock speed of 167MHz with a read latency of 1 cycle and are available in an industry standard 165-ball BGA package.
QDR SRAM was developed by the QDR Consortium, which standardized the datasheet, the package, and the performance of QDRs so that the designers can use QDRs from different vendors interchangeably.
QDRII SRAMs are similar to QDR devices in their operation but with some performance improvements. QDRII SRAMs include source-synchronous, free-running echo clocks (CQ/CQ) that enable easy data capture. QDRII SRAMs also support a 1.5 V HSTL interface.
The applications are the same as that of QDR SRAMs. However, QDRII SRAMs have a maximum speed of 333MHz with a read latency of 1.5 cycles, burst lengths of two and four, and are available in an industry standard 165-ball ball-grid array (BGA) package.
The QDR Consortium defined DDR SRAMs, which are similar to the legacy synchronous-burst SRAM products but with double data rate I/Os. Like synchronous-burst SRAMs, they are used for read-intensive functions such as packet look-up and packet classification in networking/communication applications. DDR SRAMs have a common I/O and a maximum clock speed of 167 MHz, with a read latency of one cycle. They are available in burst two and burst four flavors in industry standard 165-ball BGA package.
DDRII SRAMs are similar to DDR SRAMs in their operation but with some performance improvements. DDRII SRAMs include source-synchronous, free-running echo clocks (CQ/CQ) designed to easily capture data. DDRII SRAMs also support a 1.5V HSTL interface. The applications are the same as that of DDR SRAMs. The DDRII SRAMs have a maximum speed of 333MHz with a read latency of 1.5 cycles, burst lengths of two and four, and are available in an industry standard 165-ball BGA package.
DDRII separate I/O (SIO) SRAMs are similar to DDRII common I/O (CIO) SRAMs but they include two separate ports: a read port and a write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. DDR II SIO SRAM devices completely eliminate the need to turn around the data bus as is required with common I/O devices. DDR II SIO has separate input and output buses so this device is very similar to QDRII memory. The only difference is that DDRII SIO can perform only one operation per clock cycle. In addition, as only one bus can be used at a time, bus utilization is exactly 50%.