QDRII+ SRAMS are similar to QDRII SRAMs in their operation but with additional performance improvements. Redundant data input clocks (C & /C) are not present in QDRII devices. Instead, QDRII+ SRAMs include a handshake signal (QVLD) that indicates when the data will become valid, thereby simplifying data capture. Designers also have a choice of QDRII products with programmable on-die termination (ODT). QDRII+ SRAMs have a maximum speed of 550 MHz with read latencies of either 2 cycles or 2.5 cycles, burst length of two and four, and are available in an industry standard 165-ball BGA.
DDRII+ SRAMS are similar to DDRII SRAMs in their operation but with additional performance improvements. Redundant data input clocks (C & /C) are not present in DDRII devices. Instead, DDRII+ SRAMs include a handshake signal (QVLD) that indicates when data will become valid, thereby simplifying data capture. Designers also have a choice of QDRII products with programmable ODT. The ODT feature turns on during a write cycle and turns off during a read cycle to save power. DDRII+ SRAMs have a maximum speed of 550 MHz with read latencies of either 2 cycles or 2.5 cycles, burst length of two, and are available in an industry standard 165-ball BGA.
DDRII+ SIO SRAMs are similar to DDRII+ CIO SRAMs but they include two separate ports: a read port and a write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. DDR II+ SIO SRAM completely eliminates the need to turn around the data bus required with common I/O devices.
QDR and QDRII/QDRII+ are optimized for systems with balanced read and write operations:
- Packet memory
- Lookup Table
- Statistics Storage
DDR and DDRII/DDRII+ are optimized for data streaming operations or read/write unbalanced systems:
- L2 Cache
- Microprocessor, network processor, DSP memory
DDRII/DDRII+ SIO are I/O optimized for one address/clock two-word burst systems.
Again, QDR and QDRII/II+ are primarily used in systems with balanced reads and writes such as look-up tables and statistic storage. If caching is needed, DDR and DDRII/II+ are more suitable. If user prefers the QDR structure but cannot support a DDR interface for the address bus, then DDR with separate I/O might be the best choice.
Memory selection: Critical factors
One of the major considerations in choosing a synchronous SRAM memory is data bandwidth, which varies for the different types of synchronous SRAMs (see table 2). For the calculation, the maximum clock frequency and a bus width of x36 has been taken into account.
Table 2: Data bandwidth varies for the different types of synchronous SRAM.
Another factor in synchronous SRAM memory selection is power efficiency. The power consumption for QDR/DDR devices is lower compared to standard synchronous SRAMs due to a lower voltage supply. Other factors determining memory selection are outlined in table 3:
Click on image to enlarge
Table 3: Memory selection overview (Note: QDRII+ and DDRII+ options are offered with and without ODT.)
There are a wide variety of synchronous SRAMs offered. By understanding the different types of memory available, system designers can select the right sync memory option for their application.
About the author
Jayasree Nayar, who has a Master's degree in Electrical Engineering (VLSI design) from Santa Clara University of California, joined Cypress Semiconductor in 2003 and is a Senior Staff Applications Engineer working in Cypress' Memory and Imaging Division. Nayar’s responsibilities include creating, testing, and maintaining signal integrity and behavioral models of key products; debugging technical issues; creating documentation, application notes, and white papers; technically defining new product requirements; conducting system analysis to better understand how and where devices are being used; and board-level-failure-analysis debugging.
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