The block diagram of a simple implementation of a complete FM system using a generic FM radio chip is shown in Figure 2:
Figure 2: Block diagram of the system
With the advent of modern programmable SOCs, there is no need for any additional external components other than a few passive ones to implement the complete design. The SOC sends commands and receives status messages from the FM radio chip over an I2C port. The SOC connects to the tablet through the established USB interface. An application is used as the front-end on the tablet to access the FM radio for scanning and selecting channels.
When the FM radio receives a command to lock to a particular frequency, it outputs analog audio on specific pins. The analog output from the FM radio receiver is further processed by the SOC and the digitized audio is streamed over USB to the tablet computer. The power required for the FM radio chip operation is derived from the USB bus. The current required for most FM radio chip is typically a few milliamps or even less at 1.8V. This is well within the capability of USB bus and an acceptable level for a portable device.
The following resources are required in a SOC to implement a radio accessory:
- Analog to Digital Converter (ADC)
- Communication protocol (I2C / SPI)
- USB interface
- Filter Block
Generally, the amplitude of the output audio signal from an FM radio chip will be of the order of 100mV. An amplifier
is used for the amplification of the analog audio obtained from the FM receiver prior to feeding it to the ADC in a SOC. The strength of the analog audio output is increased after passing it through a programmable gain amplifier (PGA) as shown in the block diagram. This ensures that the entire input range of the ADC is utilized and results in a faithful reproduction of the audio at the output of the FM radio chip. It is also possible to digitize the signal by using an ADC with a smaller input range. However, the smaller the amplitude of the signal, the more vulnerable it is to system noise.
Analog to Digital Converter
(ADC) samples the analog output of the amplifier at the rate of 44.1 kHz and converts it to a 16-bit digital value. The sampling rate is chosen as 44.1 kHz which is in accordance with the Nyquist principle which states that the sampling frequency must be at least two times the maximum operating frequency.
is a standard protocol, such as I2C or SPI, that is used to interface the SOC with the FM receiver. If I2C is used, the SOC will act as the Master and the radio receiver chip will act as the slave, with a data rate of 100/400 kHz. Commands to change the channel or to scan the FM band can be issued to the FM receiver chip from the I2C master over the I2C bus. The FM receiver chip is capable of decoding predefined commands to perform various tasks. If RDS is used, then the digital information received can be read from the FM receiver by the controller using the I2C interface. It is possible to read other status information such as the RSSI from the FM radio receiver via I2C and display the same on the tablet or PC.
Direct Memory Access
(DMA) In many microcontrollers, DMA is a powerful feature that helps in offloading data transfers between memory locations to improve performance. DMA can be used to transfer the converted digital values from the ADC to memory or directly to USB while the CPU is handling other critical tasks.
is used to interface the host tablet with the SOC. A USB interrupt endpoint is used to receive various commands from the host, such as channel scan, channel increase, channel decrease, etc. Note that if the command size is small, the control endpoint on the USB device can be used to transfer commands. It is possible to use the control endpoint itself for sending commands. The commands can be sent as vendor-defined commands; however, on a control endpoint, a maximum of 8 bytes of data can be sent in one USB packet. The digital data at 44.1 kHz obtained from the ADC is transmitted to the host using Isochronous USB transfer mode. Isochronous transfer is ideal for this transmission as it is capable of maintaining consistent delivery time due to its guaranteed latency, allocated bus bandwidth, and lack of error correction and handshaking. Note that errors are detected through the CRC field but are not corrected. An occasional data error or missed transfer will not be perceived by the human ear; it takes frequent halting to reach the point of notice. As there is no error correction, there is no halt in the data transmission even in the presence of packets containing errors. A microcontroller supports a maximum packet size of 1023 bytes for an isochronous endpoint.