Some of the most critical factors to consider when choosing enterprise hardware are performance, reliability, and scalability. Dynamic random access memory (DRAM) modules affect all of these factors. IT managers have two choices of DRAM modules in platforms supporting double data rate (DDR3) protocols. These choices are error-correcting code (ECC) unregistered dual in-line memory modules (UDIMMs) and registered dual in-line memory modules (RDIMMs). In most applications, RDIMMs enable higher performance, allow better scalability, and deliver a more comprehensive set of reliability, availability, and serviceability (RAS) features than ECC UDIMMs. By using RDIMMs, companies can also reduce the total number of servers and related costs of ownership. RDIMMs are the preferred choice for most corporate application environments.
RDIMM and DDR3 registers
ECC UDIMMs are limited to applications needing up to 48-GB memories . If the estimated peak DRAM usage over time exceeds 48 GB, RDIMMs are required to avoid memory performance bottlenecks. With RDIMMs, systems are scalable to 192-GB capacities . These high capacities are possible thanks to DDR3 registers embedded in RDIMMs. The registers are specialized chips that buffer clock, command, and address signals coming from the memory controller (see figure 1). The registers allow integration of more DRAM chips in each RDIMM, and more RDIMMs per memory channel, which yields higher performance and scalability in end-applications.
Figure 1: The DDR3 register buffers clock, command, and address signals coming from the memory controller.
Table 1 describes maximum specifications for RDIMMs and ECC UDIMMs. On the application level, the use of RDIMMs with DDR3 registers translates into scalable systems with predictable performance over time.
Table 1: Maximum specifications for RDIMMs and ECC UDIMMs in servers using the Xeon processor 5500 series
To better understand how DDR3 registers enable higher performance and quadruple memory capacity when compared to ECC UDIMMs, it is necessary to examine how memory modules impact line loading. Each memory module, whether RDIMM or ECC UDIMM, communicates with a memory controller via data (DQ), data strobe (DQS), address, command, clock, and chip select signals. Using a real module design example, a 16-GB RDIMM containing 36 4-Gb DRAM chips and including four DRAMs for error correction is organized in four ranks of nine DRAM chips each. A memory rank is a group communicating over the 72-bit data bus of a memory module, independently selectable via the chip select (CS) signal.
Reviewing the block diagram of the example above (see figure 2), it’s notable that the memory controller has one load at the DDR3 register on each clock, command, address, and CS line, and four loads on the DQ and DQS lines. Without the DDR3 register, the controller would see nine loads on the CS lines. Furthermore, clock, command, and address loads increase drastically to 36 due to the direct connection to DRAM chips. These higher loadings would cause the memory controller to fail to communicate at a high speed. For this reason, ECC UDIMM modules are typically limited to a DRAM capacity that is a factor of four times smaller than for RDIMM (see table 2).
Figure 2: 16-GB RDIMM architecture with DDR3 register
Table 2: Loading of memory controller lines with and without DDR3 register