Traditional IC pattern-generation methods focus on detecting defects at gate terminals or at interconnects. Unfortunately, a significant population of defects may occur within an IC's gates, or cells. Many internal defects in cells can be detected with traditional test methods, but some require a unique set of stimulus to excite and observe the defect. A cell-aware ATPG (automatic test pattern generation) method performs a characterization of the library cell's physical design to produce a set of UDFMs (user-defined fault models). Thus, the actual cell-internal physical characteristics are used to define and target faults.
In addition to explaining how cell-aware ATPG works, this article includes published simulation results from two major IC companies to highlight the test method. Production silicon test results using cell-aware UDFM have shown notable improvement in DPM (defects-per-million) beyond what stuck-at and transition patterns detect. As a result of this significant impact in DPM, cell-aware UDFM is beginning to get a lot of attention in the industry.
Follow the jump directly to the article on our sister publication, Test & Measurement World. Topics covered include: history of IC test, cell-aware ATPG, cell-aware characterization flow, industrial results, choosing the best tests, and adaptive test for production.
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