Traditional IC pattern-generation methods focus on detecting defects at gate terminals or at interconnects. Unfortunately, a significant population of defects may occur within an IC's gates, or cells. Many internal defects in cells can be detected with traditional test methods, but some require a unique set of stimulus to excite and observe the defect. A cell-aware ATPG (automatic test pattern generation) method performs a characterization of the library cell's physical design to produce a set of UDFMs (user-defined fault models). Thus, the actual cell-internal physical characteristics are used to define and target faults.
In addition to explaining how cell-aware ATPG works, this article includes published simulation results from two major IC companies to highlight the test method. Production silicon test results using cell-aware UDFM have shown notable improvement in DPM (defects-per-million) beyond what stuck-at and transition patterns detect. As a result of this significant impact in DPM, cell-aware UDFM is beginning to get a lot of attention in the industry.
Follow the jump directly to the article on our sister publication, Test & Measurement World. Topics covered include: history of IC test, cell-aware ATPG, cell-aware characterization flow, industrial results, choosing the best tests, and adaptive test for production.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.