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Automatic C-to-VHDL testbench generation shortens FPGA development time

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dorecchio
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re: Automatic C-to-VHDL testbench generation shortens FPGA development time
dorecchio   4/12/2012 1:06:34 PM
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Any approach that raises the level of abstraction for design of the new SoC FPGAs is a good thing. Automating the flow through the design process is even better. I like the work that Impulse and Aldec have done here.

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