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How to select the right timing device--A case for MEMS—Part I

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steve5500
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re: How to select the right timing device--A case for MEMS—Part I
steve5500   4/20/2012 4:41:01 AM
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Regarding phase noise contributions and low-frequency offsets; it is correct that jitter contribution at low offset frequencies cannot be ignored, and that was not the intended point in this article. The confusion seems to be in definition of “corner frequency”. The corner frequencies cited in the article refer to the 3dB upper and lower cutoff frequencies of a bandpass filter. The attenuation in stop-band is 20dB/dec for most standards, as the reader noted. The integration range is typically much larger than pass-band frequency range of the filter, for example, 100Hz to 50MHz (or half the clock rate). The full details can be found in SiTime application note AN10012: http://www.sitime.com/support2/documents/AN10012_SerialIO_PhaseJitterReguirement_rev1.2.pdf. The 12kHz to 20MHz integration range does not assume any smooth filtering of phase noise outside that range; it totally ignores any phase noise outside that range. It is true that for cases that 12kHz to 20MHz phase jitter is low, the filtering response of the application can be ignored because the noise outside the application filter pass-band would be small. Nevertheless, the application filter response is the one governing the jitter budgeting of the application and 12kHz to 20MHz integrated phase jitter is merely a proxy that has been widely used in practice. SiTime's new class of LVCMOS, LVPECL, and LVDS devices meet low typical phase jitter of 0.5ps (0.85ps max) integrated from 12kHz to 20MHz. The user can easily use these parts regardless of analysis method used. The standard governing phase jitter filtering and budgeting has been developed for a long time with careful attention to different trade-offs. One of important jitter documents for serial-IOs is MJSQ that was generated for Fibre Channel applications. To my knowledge, the MJSQ does not make any assumption about the oscillator source. Steve Pratt SiTime Marketing

steve5500
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re: How to select the right timing device--A case for MEMS—Part I
steve5500   4/20/2012 4:34:44 AM
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The need for low wander (phase jitter below 10Hz) in telecom (SDH/SONET) applications and convergence of telecom and networking through Synchronous Ethernet is expected to increase demand for parts with low wander. This is true. The topic of wander was not addressed becasue it's beyond the scope of this article. The question is whether MEMS oscillators can deliver on that, and the answer is yes. SiTime has published phase noise plots on their website (starting from 1kHz offset) for specific frequencies. In addition, SiTime provides phase noise plots down to 1Hz for any specific frequency that a customer may request. As a guideline, the RMS wander for SiTime's SiT8208/9 and SiT912x single-ended and differential MEMS-based oscillator products is 1.5UI rms (phase jitter between 1Hz to 10Hz). This easily meets the 2490UI tolerance limit the reviewer mentions. Furthermore, SiTIme's upcoming MEMS-based Stratum-3 devices will meet all MTIE and TDEV requirement for synchronous networks. Steve Pratt SiTime Marketing

psevalia
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re: How to select the right timing device--A case for MEMS—Part I
psevalia   4/20/2012 12:50:13 AM
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Hi Ron - are you the Director of Sales and Marketing at Q-Tech Corporation, a supplier of quartz crystal oscillators? http://www.q-tech.com/contact.html If so, I completely understand your perspective. Please do see my comment below on how SiTime is providing correct data and information to our customers for them to make an informed decision. Best regards Piyush Sevalia VP, Marketing, SiTime Corp. psevalia@sitime.com 408-331-9138 www.sitime.com

psevalia
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re: How to select the right timing device--A case for MEMS—Part I
psevalia   4/19/2012 10:15:12 PM
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Hi Ron Stephens - the Pletronics article that you refer to, compares quartz oscillators with a first generation MEMS oscillator that was originally released in 2006, 6 years ago. Four subsequent generations of MEMS oscillators have shown dramatic improvements in performance. In addition to the information in this article, please look at the technology section of the SiTime website. http://www.sitime.com/company/technology-overview/overview Some performance specs of SiTime’s recent MEMS oscillators are: 500 fs of integrated RMS Phase jitter from 12 kHz to 20 MHz (SONET Standard) 5 PPB of Allan Deviation (short term frequency stability) which is about 500 times better than what was referred to in the Pletronics article. Please look at the datasheets of SiT820x, SiT500x, SiT912x, SiT530x for more details. If you register on the SiTime website, you will also have access to performance measurement reports, here. http://www.sitime.com/support/performance-measurement-report These reports show measurements of specs for different frequencies such as phase noise, Phase jitter and period jitter, rise and fall time and duty cycle. Also - if you have access to IEEE or ISSCC proceedings, please look at the ISSCC paper Session 11.6, presented on Thursday, Feb 21, 2012 for details on implementation on our new MEMS oscillators. In the future, do look out for information on Resilience - how MEMS oscillators outperform Quartz on PSRR, Vibration Tolerance, EMI susceptibility and overall reliability. This information will be published on our website in the next 2 weeks and contains detailed results. SiTime offers as much information as you need to make a decision on selecting the right timing component for your design. If you do not find this information on our website, then please do contact us at salessupport@sitime.com. We'd be happy to provide you with what you need. Piyush Sevalia VP, Marketing, SiTime Corp. psevalia@sitime.com 408-331-9138

CMathas
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re: How to select the right timing device--A case for MEMS—Part I
CMathas   4/19/2012 6:00:57 PM
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See replies from the author on Part II of the article at http://www.eetimes.com/design/communications-design/4371124/How-to-select-the-right-timing-device-Part-II?Ecosystem=analog-design

awaretek
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re: How to select the right timing device--A case for MEMS—Part I
awaretek   4/19/2012 4:08:56 PM
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As Mathew Isaacs points out above, this article is very misleading, in that it shows only data favorable to MEMS resonators and avoids the large and serious disadvantages of MEMS vs. quartz resonators. In fact, MEMS have such terrible short term stability that MEMS manufacturers like SiTime avoid the subject entirely. It turns out that MEMS resonators have problems for which there were previously no specifications defined, since quartz simply doesn't have those particular problems, such as extremely large numbers of continual frequency jumps as large as 1 PPM. That's why MEMS Manufacturers like the authors always like to talk about averages, such as integrated phase jitter (with carefully chosen ranges to show "good" results), instead of showing a good old fashioned phase noise plot that would show the horrible phase noise performance of MEMS, particularly close in to the carrier where it often matters most. The reason is because MEMS have much lower "Q" or quality factor, than quartz, which is why quartz has always been used for precision time and frequency instead of mechanical resonators. A more balanced source of information can be found at http://www.pletronics.com/ple/pages/documentation (I have no affiliation with Pletronics, the publisher of the data sheets such as AN# 801: Comparative Analysis: MEMs versus Traditiional Quartz Oscillators - that offers a balanced comparison of the two technologies. It is unfortunate that marketing so often over-rides engineering and common sense these days. Ron Stephens

Matthew.Isaacs
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re: How to select the right timing device--A case for MEMS—Part I
Matthew.Isaacs   4/15/2012 9:47:46 PM
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Serial link standards that recognize the reality of low-frequency jitter accumulation in multi-hop links have been developed. Examples include ITU-T SDH requirements for STM-64 links, which requires 10Gbps receivers to handle up to 2490 UI of jitter at 10Hz modulation frequency. As datacomm is now attempting to become like SONET & SDH in terms of being able to share timing across the network by passing it along from one node to the next in a long chain, the considerations of low-offset phase noise are becoming extremely important for both traditional telecom and datacomm. All of this means that those who advocate MEMS over quartz should at least publish a phase noise plot in their attempts to produce a case that MEMS can provide an acceptable replacement to quartz-based oscillators. Even better would be for them to publish test results of "wander" -- meaning jitter below 10Hz. With the communications industry's seismic shift towards synchronized networking to support realtime audio & video, this is the hot topic, not high-frequency jitter, which has already been conquered by the venerable 10 cent quartz crystal & a sub-cent oscillator circuit contained within any IC that may need a clock. I should note that unlike the authors, whose jobs appear to rely upon selling MEMS, I have no financial ties to anything in the quartz realm -- I simply need to be able to use a clock that works.

Matthew.Isaacs
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re: How to select the right timing device--A case for MEMS—Part I
Matthew.Isaacs   4/15/2012 9:46:19 PM
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This article fails to note that integration range is not necessarily related to corner frequency. Just because the corner frequency is at 1 MHz does not mean that jitter below that frequency can be ignored in the least. In fact, because many common RX circuits in high-speed serial links implement only a first order filter, and due to a digital frequency architecture that does not have the sensitivity necessary to respond to low or slow frequency changes, the jitter might grow much more quickly at lower offset frequencies than the clock recovery can possibly track, resulting in an eye closure or bit-error ratio penalty. For example, 10UI of jitter at 1/100th of the corner frequency of a receiver's tracking bandwidth is as damaging to the bit error ratio of a first-order receiver at 0.1UI of jitter above the corner frequency. For most quartz-based clocks, low frequency clock jitter can be conveniently ignored entirely, particularly if the clock is shared by circuits on both ends of a (short / low-delay) serial link. However, many serial link standards assumed quartz crystal based performance when the jitter tolerance requirements were developed. This is particularly true for point-to-point datacom standards. If in fact low frequency jitter is more significant than obtained using quartz-based oscillators, these assumptions are not valid, and the standard is incapable of providing adaquate guidance in terms of either system design or test conformance.

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