Editor's Note: This article first appeared in the Second Quarter 2012 issue of Xcell Journal, and is reproduced here with the kind permission of Xilinx (Click Here to see a PDF of the full issue).
After four years of development and a year of beta testing, Xilinx is making its Vivado Design Suite available to customers via its early-access program, ahead of public access this summer. Vivado provides a highly integrated design environment with a completely new generation of system- to IC-level tools, all built on the backbone of a shared scalable data model and a common debug environment. It is also an open environment based on industry standards such as the AMBA AXI4 interconnect, IP-XACT IP packaging metadata, the Tool Command Language (Tcl), Synopsys Design Constraints (SDC) and others that facilitate design flows tailored to the users’ needs. Xilinx architected the Vivado Design Suite to enable the combination of all types of programmable technologies and to scale up to 100 million ASIC equivalent-gate designs.
“Over the last four years, Xilinx has pushed semiconductor innovation to new heights and unleashed the full system-level capabilities of programmable devices,” said Steve Glaser, senior vice president of corporate strategy and marketing. “Over this time, Xilinx has evolved into a company that develops All Programmable Devices, extending programmability beyond programmable logic and I/O to software-programmable ARM subsystems, 3D ICs and analog mixed signal. We are enabling new levels of programmable system integration with devices such as the award-winning Zynq-7000 Extensible Processing Platform, the 3D Virtex-7 stacked-silicon interconnect (SSI) technology devices and the world’s most advanced FPGAs. Now, with Vivado, we are offering a state-of-the-art tool suite that will accelerate the productivity of customers using these All Programmable Devices for the next decade.”
Glaser said Xilinx developed All Programmable Devices to enable customers to achieve new levels of programmable systems integration, increased system performance, lower BOM cost and total system power reduction, and ultimately to accelerate design productivity so they can get their innovations to market quickly. To accomplish this, Xilinx needed to create a tool suite as innovative as its new silicon—a suite that would address nagging integration and implementation design-productivity bottlenecks.“Customers face a number of integration bottlenecks, including integrating algorithmic C and register-transfer level (RTL) IP; mixing the DSP, embedded, connectivity and logic domains; verifying blocks and ‘systems’; and reusing designs and IP,”
said Glaser. “They also face several implementation bottlenecks, including hierarchical chip planning and partitioning; multidomain and multidie physical optimization; multivariant ‘design’ vs. ‘timing’ closure; and late ECOs and the rippling effects of design changes. The new Vivado Design Suite addresses these bottlenecks and empowers users to take full advantage of the system integration capabilities of our All Programmable Devices.”
In developing the Vivado Design Suite, Xilinx leveraged industry standards and employed state-of-the-art EDA technologies and techniques. The result is that all designers—from those who require a highly automated, pushbutton flow to those who are extremely hands-on—will be able to design even the largest Xilinx devices far faster and more effectively than before, while working in a state-of-the-art EDA environment that retains a familiar, intuitive look and feel.
The Vivado Design Suite gives customers a modern set of tools with full-system programmability features that far surpass the capabilities of the longtime flagship ISE Design Suite. To help customers transition smoothly, Xilinx will continue to develop and support ISE indefinitely for those targeting 7 series and older Xilinx FPGA technologies. Going forward, the Vivado Design Suite will be the company’s flagship design environment, supporting all 7 series and future devices from Xilinx.
Tom Feist, senior director of design methodology marketing at Xilinx, expects that when customers launch the Vivado Design Suite, the benefits over ISE will become immediately evident.“The Vivado Design Suite improves user productivity by offering up to 4X runtime improvements over competing tools, while heavily leveraging industry standards such as SystemVerilog, SDC, C/C++/SystemC, ARM’s AMBA AXI version 4 interconnect and interactive Tcl scripting,”
said Feist. “Other highlights include comprehensive cross-probing of the Vivado’s many reports and design views, state-of-the-art graphics-based IP integration and, last but not least, the first fully supported commercial deployment of high-level synthesis—C++ to HDL—by an FPGA vendor.” Tools for the next era of programmable design
Xilinx originally introduced its ISE Design Suite back in 1997. The suite featured a then very innovative timing-driven place-and-route engine that Xilinx had gained in its April 1995 acquisition of NeoCAD. Over a decade and a half, Xilinx added numerous new technologies—including multilanguage synthesis and simulation, IP integration and a host of editing and test utilities—to the suite, striving to constantly improve its design tools on all fronts as FPGAs became capable of performing increasingly more complex functions. In creating the new Vivado Design Suite, Feist said that Xilinx drew upon all the lessons learned with ISE, appropriating its key technologies while also leveraging modern EDA algorithms, tools and techniques.“The Vivado Design Suite will greatly improve design productivity for today’s designs and will easily scale for the capacity and design-complexity challenges of 20-nanometer silicon and beyond,”
said Feist. “EDA technology has evolved greatly over the last 15 years. In building this tool from scratch, we were able to create a suite that employs the latest EDA technologies and standards and will scale nicely into the foreseeable future.”Deterministic design closure
At the heart of any FPGA vendor’s integrated design suite is the physical-implementation flow—synthesis, floorplanning, placement, routing, power and timing analysis, optimization and ECO. With Vivado, Xilinx has built a state-of-the-art implementation flow to help customers quickly achieve design closure. Scalable data model architecture
To cut down on iterations and overall design time and to improve overall productivity, Xilinx built its implementation flow using a single, shared, scalable data model—a framework also found in today’s most advanced ASIC design environments. “This shared scalable data model allows all the steps in the flow—synthesis, simulation, floorplaning, place and route, etc.—to operate on an in-memory data model that enables debug and analysis at every step in the process, so that users have visibility into key design metrics such as timing, power, resource utilization and routing congestion much earlier in the design processes,”
said Feist. “These estimates become progressively more accurate as the design progresses through the steps in the implementation processes.”
Specifically, the unified data model allowed Xilinx to tightly link its new multidimensional, analytical place-and-route engine with the suite’s RTL synthesis engine, new multiple-language simulation engines as well as individual tools such as the IP Integrator, Pin Editor, Floor Planner and Device Editor. Customers can use the tool suite’s comprehensive cross-probing function to track and cross-probe a given problem from schematics, timing reports or logic cells to any other view and all the way back to HDL code.“You now have analysis at every step of the design process and every step is connected,”
said Feist. “We also provide analysis for timing, power, noise and resource utilization at every stage of the flow after synthesis. So if I learn early that my timing or power is way off, I can do short iterations to address the issue proactively rather than run long iterations, perhaps several of them, after it’s been placed and routed.”
Feist said that tight integration afforded by the scalable data model enhanced the effectiveness of pushbutton flows for users who want maximum automation, relying on their tools to do the vast majority of the work. At the same time, he said, it also gives those users who require more-advanced controls better analysis and command of their every design move.Hierarchical chip planning, fast synthesis
Feist said that Vivado provides users with the ability to partition the design for processing by synthesis, implementation and verification, facilitating a divide-and-conquer team approach to big projects. A new design-preservation feature enables repeatable timing results and the ability to perform partial reconfiguration of the design.
Vivado also includes an entirely new synthesis engine that is designed to handle millions of logic cells. Key to the new synthesis engine is superior support for SystemVerilog. “Vivado’s synthesis engine supports the synthesizable subset of the SystemVerilog language better than any other tool in the market,”
said Feist. It is three times faster than XST, the Xilinx Synthesis Technology in the ISE Design Suite, and supports a “quick” option that lets designers rapidly get a feeling for the area and size of the design, allowing them to debug issues 15 times faster than before with an RTL or gate-level schematic. With more and more ASIC designers moving to programmable platforms, Xilinx is also leveraging Synopsys Design Constraints throughout the Vivado flow. The use of standards opens up new levels of automation where customers can now access state-of-the-industry EDA tools for things like constraint generation, cross-domain clock checking, formal verification and even static timing analysis with tools like PrimeTime from Synopsys.Multidimensional analytical placer
Feist explained that the older-generation FPGA vendor design suites use one-dimensional timing-driven place-and-route engines powered by simulated annealing algorithms that determine randomly where the tool should place logic cells. With these routers, users enter timing; then the simulated annealing algorithm pseudorandomly places features to get a “best as it can” match to timing requirements. “In those days it made sense, because designs were much smaller and logic cells were the main cause of delays,”
said Feist. “But today, with complex designs and advances in silicon processes, interconnect and design congestion contribute to the delay far more.”
Place-and-route engines with simulated annealing algorithms do an adequate job for FPGAs below 1 million gates, “but they really start to underperform as designs grow,” said Feist. “Not only do they struggle with congestion, but the results start to become increasingly more unpredictable as designs grow further beyond 1 million gates.”
With an eye toward the multimillion-gate future, Xilinx developed a modern multidimensional analytic placement engine for the Vivado Design Suite that is on par with those found in million-dollar ASIC place-and-route tools. This engine analytically finds a solution that primarily minimizes three dimensions of a design: timing, congestion and wire length. “The Vivado Design Suite’s algorithm globally optimizes for best timing, congestion and wire length simultaneously, taking into account the entire design instead of the local-move approach done with simulated annealing,”
said Feist. “As a result, the tool can place and route 10 million gates quickly, deterministically and with consistently strong quality of results” (see Figure 1). “Because it is solving for all three factors simultaneously, it means you run fewer iterations in your flow.”
Figure 1. The Vivado Design Suite implements large and
small designs more quickly and with better-quality
results than other FPGA tools.
To illustrate this advantage, Xilinx ran the raw RTL for the Zynq-7000 EPP emulation platform, a very large and complex design, in both the ISE Design Suite and Vivado Design Suite in a pushbutton mode. Each tool was instructed to target Xilinx’s largest FPGA device—the SSI-enabled Virtex-7 2000T FPGA. The Vivado Design Suite’s place-and-route engine took five hours to place the 1.2 million logic cells, while the ISE Design Suite version 13.4 took 13 hours (Figure 2). The Vivado Design Suite also implemented the design with much less congestion (as seen in the gray and yellow portions of the design) and in a smaller area, reflecting the total wire-length reduction. In addition, the Vivado Design Suite implementation had better memory compilation efficiency, taking only 9 Gbytes to implement the design’s required memory to ISE Design Suite’s 16 Gbytes.
Figure 2. The Vivado Design Suite’s multidimensional “Essentially what you’re seeing is that the Vivado Design Suite met all constraints and only needed three-quarters of the device to implement the entire design,”
analytic algorithm optimizes layouts for best timing,
congestion and wire length, not just best timing.
said Feist. “That means users could add even more logic functionality and on-chip memory to their designs [in the extra space] or, alternatively, even move to a smaller device.”Power optimization and analysis
Today, power is one of the most critical aspects of FPGA design. As such, the Vivado Design Suite focuses on advanced power-optimization techniques to provide greater power reductions for users’ designs. “The technology uses advanced clock-gating techniques found in today’s advanced ASIC tool suites and is capable of analyzing design logic and removing unnecessary switching activity by applying clock gating,”
said Feist. “Specifically, the new technology focuses on the switching-activity factor ‘alpha.’ It is able to achieve up to a 30 percent reduction in dynamic power.”
Feist said Xilinx introduced the technology in the ISE Design Suite last year but is carrying it forward and will continue to enhance it in Vivado.
In addition, with the new shared scalable data model, users can get power estimates at every stage of the design flow, enabling up-front analysis so that problem areas can be addressed early in the design flow, said Feist.Simplifying engineering change orders
Incremental flows make it possible to quickly process small design changes by simply reimplementing a small part of the design, making iterations faster after each change. They also enable performance preservation after each incremental change, thus reducing the need for multiple design iterations. Toward this end, the Vivado Design Suite includes a new extension to the popular ISE FPGA Editor tool called the Vivado Device Editor. Feist said that using the Vivado Device Editor on a placed-and-routed design, designers now have the power to make engineering change orders (ECOs)—to move instances, reroute nets, tap a register to a primary output for debug with a scope, change the parameters on a digital clock manager (DCM) or a lookup table (LUT)—late in the design cycle, without needing to go back through synthesis and implementation. No other FPGA design environment offers this level of flexibility, he said.Flow automation, not flow dictation
In building the Vivado Design Suite, the Xilinx tool team’s mantra was to automate—not dictate—the way people design. “Whether they start in C, C++, SystemC, VHDL, Verilog or SystemVerilog, MATLAB or Sim¬ulink—and whether they use our IP or third-party IP—we offer a way to automate all those flows and help customers be more productive,”
said Feist. “We also accounted for the broad range of skill sets and preferences of our users—from folks who want an entirely pushbutton flow to folks who do analysis at each phase of the design, and even for those who think GUIs are for wimps and want to do everything in command-line or batch mode via TCL. Users are able to suit the suite’s features to their specific needs.”The IP packager, integrator, and catalog
Xilinx’s tool architecture team placed top priority on giving the new suite specialized IP features to facilitate the creation, integration and archiving of intellectual property. To this end, Xilinx has created three new IP capabilities in Vivado, called IP Packager, IP Integrator and the Extensible IP Catalog.“Today, it is hard to find an IC design that doesn’t incorporate some amount of IP,”
said Feist. “By adopting industry standards and offering tools to specifically facilitate the creation, integration and archiving/upkeep of IP, we are helping IP vendors in our ecosystem and customers to quickly build IP and improve design productivity. More than 20 vendors are already offering IP supporting the new suite.”
IP Packager allows Xilinx customers, IP developers and ecosystem partners to turn any part of their design—or indeed, the entire design—into a reusable core at any level of the design flow: RTL, netlist, placed netlist and even placed-and-routed netlist. The tool creates an IP-XACT description of the IP that users can easily integrate into future designs. For its part, the IP Packager specifies the data for each piece of IP in an XML file. Feist said that once you have the IP packaged, you can use the new IP Integrator to stitch it into the rest of your design.“IP Integrator allows customers to integrate IP into their designs at the interconnect level rather than at the pin level,”
said Feist. “You can drag and drop the pieces of IP onto your design and it will check up front that the respective interfaces are compatible. If they are, you draw one line between the cores and it will automatically write the detailed RTL that connects all the pins.”
Once you’ve merged, say, four or five blocks into your design with IP Integrator, he said, “you can take the output of that [process] and run it back through the IP Packager.”
The result “then becomes a piece of IP that other people can reuse,”
said Feist. “And this IP isn’t just RTL, it can be a placed netlist or even a placed-and-routed IP netlist block, which further saves integration and verification time.”
A third feature, the Extensible IP Catalog, allows users to build their own standard repositories from IP they’ve created or licensed from Xilinx and third-party vendors. The catalog, which Xilinx built to conform to the requirements of the IP-XACT standard, allows design teams and even enterprises to better organize their IP and share it across their organization. Feist said that the Xilinx System Generator and IP Integrator are part of the Vivado Extensible IP Catalog so that users can easily access catalogued IP and integrate it into their design projects.“Instead of having third-party IP vendors deliver their IP in a zip file and with various deliverables, they can now deliver it to you in a unified format that is instantly accessible and compatible with the Vivado suite,”
said Ramine Roane, director of product marketing for Vivado.Vivado HLS takes ESL mainstream
Perhaps the most forward looking of the many new technologies in the Vivado Design Suite release is Vivado HLS (high-level synthesis), which Xilinx gained in its acquisition of AutoESL in 2010. Xilinx conducted an extensive evaluation of commercial electronic system-level (ESL) design offerings before acquiring the best in the industry. A study by research firm BDTI helped Xilinx’s acquisition choice (see Xcell Journal issue 71
, “BDTI Study Certifies High-Level Synthesis Flows for DSP-Centric FPGA Design”
).“Vivado HLS provides comprehensive coverage of C, C++ and SystemC, and does floating-point as well as arbitrary precision floating-point [calculations],”
said Feist. “This means that you can work with the tool in an algorithm-development environment rather than a typical hardware environment, if you wish. A key advantage of doing this is that the algorithms you developed at that level can be verified orders of magnitude faster than at the RTL. That means you get simulation acceleration but also the ability to explore the feasibility of algorithms and make, at an architectural level, trade-offs in terms of throughput, latency and power.”
Figure 3. Vivado HLS allows design teams
to begin their designs at a system level.
Designers can use the Vivado HLS tool in many ways to perform a wide range of functions. But for demonstration purposes, Feist outlined a common flow users can employ for developing IP and integrating it into their designs.
In this flow, users create a C, C++ or SystemC representation of their design and a C testbench that describes its desired behavior. They then verify the system behavior of their design using a GNU Compiler Collection/G++ or Visual C++ simulator. Once the behavioral design is functioning satisfactorily and the accompanying testbench is ironed out, they run the design through Vivado HLS synthesis, which will generate an RTL design: Verilog or VHDL. With the RTL they can then perform Verilog or VHDL simulation of the design or have the tool create a SystemC version using the C-wrapper technology. Users can then perform SystemC architectural-level simulation and further verify the architectural behavior and functionality of the design against the previously created C testbench.
Once the design has been solidified, users can put it through the Vivado Design Suite’s physical-implementation flow to program their design into a device and run it in hardware. Alternatively, they can use the IP Packager to turn the design into a reusable piece of IP, stitch the IP into a design using IP Integrator or run it in System Generator.
This is merely one way to use the tool. In fact, in this issue of Xcell Journal, Agilent’s Nathan Jachimiec and Xilinx’s Fernando Martinez Vallina describe how they used the Vivado HLS technology (called AutoESL technology in the ISE Design Suite flow) to develop a UDP packet engine for Agilent. Vivado simulator
In addition to Vivado HLS, Xilinx also created a new mixed-language simulator for the suite that supports Verilog and VHDL. With a single click of the mouse, Feist said, users can launch behavioral simulations and view results in an integrated waveform viewer. Simulations are accelerated at the behavioral level using a new performance-optimized simulation kernel that executes up to three times faster than the ISE simulator. Gate-level simulations can also run up to 100 times faster using hardware co-simulation.Availability in 2012
Where Xilinx offered the ISE Design Suite in four editions aimed at different types of designers (Logic, Embedded, DSP and System), the company will offer the Vivado Design Suite in two editions. The base Design Edition includes the new IP tools in addition to Vivado’s synthesis-to-bitstream flow. Meanwhile, the System Edition includes all the tools of the Design Edition plus System Generator and Xilinx’s new Vivado HLS.
The Vivado Design Suite version 2012.1 is available now as part of an early-access program. Customers should contact their local Xilinx representative for more information. Public access will commence with version 2012.2 in the middle of the second quarter, followed by WebPACK availability later in the year. ISE Design Suite Edition customers with current support will receive the new Vivado Design Suite Editions in addition to ISE at no additional cost.
Xilinx will continue to support and develop the ISE Design Suite for customers targeting devices prior to the 28-nm generation. To learn more about Vivado, please visit www.xilinx.com/design-tools or come see the suite in action at the Design Automation Con-ference (DAC), June 3-7 in San Francisco, Booth 730.About the author
Mike Santarini is the publisher of the Xilinx Xcell Journal. Mike can be contacted at firstname.lastname@example.org
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