The advent of 802.3ap Backplane Ethernet and its low-cost implementation at 10 Gbits/second, 10GBase-KR, has forever changed the way system designers think about the next generation of backplanes. While 10GBase-KR originally was promoted as a network-infrastructure backplane to migrate 10G networks to 40G and 100G Ethernet, it now finds greater utility as a backplane for servers and industrial platforms requiring multi-gigabit bandwidth. As systems demand interfaces capable of handling four-channel and 10-channel paths to 40/100G Ethernet, universal adoption of 10GBase-KR seems likely.
Although 10GBase-KR is a single-channel copper backplane operating at 10.3125 Gbits/s, the ease in implementing four channels has led some system vendors to look upon the single-channel backplane as the ideal stepping-stone for four-channel 40G Ethernet implementations. In the near future, experience gained in 10-Gbit multiple channels will allow 10-channel 100G Ethernet, supported by the current C form-factor pluggable (CFP) and extended-capability pluggable (CXP) modules. Eventually, the availability of faster chip-level transceivers and experience with faster board-level channels will allow four-channel 100G Ethernet, with each channel supporting up to 28 Gbits/s (25 Gbits plus forward error correction overhead). That standard will use the emerging CFP2 multisource agreement (CFP2 MSA) module.
But there are speed bumps on the path to ubiquitous 40G and 100G Ethernet. Network equipment developers who worked with 10G Sonet/OTN or first-generation 10G Ethernet design have experienced firsthand how difficult the maintenance of signal quality can be as backplanes move from 2 or 3 Gbits/s to 10 Gbits/s. The discontinuities brought about by high-speed signal integrity challenges have a pronounced impact on the choice of pc board substrate materials and board layout methodology.
Although EDA tools for both simulation and place-and-route have improved significantly in the past two decades, the system designer must play an active role in ensuring high-speed signal fidelity at both the device and board levels simultaneously. On a lower level of discrete devices, system designers must be fully cognizant of the equalization and error-correction parameters of individual chips, particularly the receivers and transmitters in the high-speed paths.
At the same time, however, the board-level designer must keep in mind the implications of the layout of high-speed traces (including vias), edge rates and planar discontinuities. Unless the whole-system approach is kept paramount, planning for such contingencies can amount to a game of Whac-A-Mole: Optimize a design for one transceiver channel, and unacceptable compromises pop up elsewhere.
|Figure 1. Failure to manage pc board traces can lead to significant noise impacts, as observed through the closure of eye diagrams.|
Physical layout of the board must take into account via stubsí potential for significantly degrading signal integrity. Backdrilling is highly recommended to mitigate the unwanted high-frequency resonances caused by via stubs. Board layout can also be affected by the type of data encoding used by physical-layer and PHY/MAC combo chips.
If devices are laid out randomly, with little concern for trace positioning, signals can be subject to high-frequency crosstalk and impedance discontinuities, which cannot always be alleviated through equalization.