The optimized MTJ structures were patterned from sub-20-nm to 65-nm size as a short axis dimension using a special etch technique (Figure 7). Junction sizes were measured by TEM and SEM images.
Figure 7: Cross-sectional TEM image of 17-nm MTJ. The length of the short axis is about 17 nm.
Figure 8 shows R-H distribution of MTJ cells with the sizes of <17 × 40 nm2
>, <20 × 40 nm2
>, <40 × 90 nm2
> and <65 × 95 nm2
>. For compensating stray field from pinned layers, R-H curves were measured with external fields up to 600 Oe. As the size of MTJs decreases from 65 nm to 17 nm, the 1σ
of Hc distribution increases from 3% to 8.8%. In order to exclude the multi-domain effect, Δ has been obtained from Hc distribution in the repeated R-H measurements .
Figure 8: R-H distribution of a single cell switching at the size of (a) 17-nm, (b) 20-nm, (c) 40-nm, and (d) 65-nm cell size, respectively.
The thermal energy barrier has been extracted by equation (1) with cumulative probability of field switching being plotted as a function of applied field.
Figure 9 shows cumulative switching probability at 100 time repeated R-H measurements. The measurement results show a good agreement with calculated Hc distributions.
Figure 9: Fittings of Hc obtained in figure 8 to extract thermal stability factor. Inset shows fitted Hc of MTJs patterned by process A and B, resulting in thermal stability factor of 44 and 71, respectively.
Figure 10 shows Δ values of the MTJs extracted from equation (1). Δ has a linear dependence on the MTJ cell volume as speculated by its definition. As a result, in the inset of figure 10, patterned MTJ cells were found to have two different trend lines of Δ ~44 and ~70 with different processes (P-A, P-B) at the 40-nm scale. From the Δ value for P-A, retention time at sub-20-nm MTJ is estimated at around 3.5 days. Sufficient data retention over 10 years at a gigabit density array may be attainable with the improved P-B.
Figure 10: Thermal stability factor (E/Kb*t) as a function of patterned MTJ cell area.
Figure 11 shows STT switching at 100ns pulse. The measurement is repeated 100 times. 1σ of VSW
(+) and (-) are 5.6% and 4.9%.
Figure 11: STT switching curves of single cell measured 100 times at the pulse width of 100 ns.
Figure 12 shows the dependency of STT switching probability on injected current. STT Ic for 100% writing at a 100-ns pulse is less than 47 µA.
Figure 12: Switching probability of figure 11.
Figure 13 shows measured Ic as a function of the storage layer area. STT Ic as a function of storage layer area shows linear dependency.
Figure 13: Switching current (Ic) as a function of MTJ cell area at the pulse width 100 ns.
For the evaluation of switching region, normalized switching phase diagram (nSPD) for a 17-nm MTJ cell at 300K was investigated (Figure 14).
Figure 14: Normalized switching phase diagram of 17 nm MTJ cell at 300K.
In the first quadrant (Hext>0 and VSW>0), STT favors the P-to-AP switching, whereas, in the third quadrant (Hext<0 and VSW<0), STT favors the AP-to-P switching. These results of Ic and Δ behavior as a function of storage layer area demonstrate that it is possible to maintain high Δ and low Ic as the MTJ cell size decreases. MTJs of sub-20-nm scale are anticipated to be in a single domain state. However, because of extrinsic factors involved in MTJ fabrication, the change of Δ and Ic exhibits multi-domain features at sub-20-nm sized MTJ above aspect ratio 2. The major difference between P-A and P-B occurs at the node separation process. Thus it is particularly important to further investigate the extrinsic effects of integration process on Δ.
Downscaling feasibility of STT-MRAM has been investigated by patterning perpendicular MTJ cells of 17-nm feature size. Enhanced i-PMA with precisely engineered interfaces and improved integration processes including a novel etch process have been combined to achieve reproducible STT switching of P-MTJ cells at sub-20-nm node. Although electrical performances of the sub-20-nm MTJ cells currently require further improvements for future gigabit-density non-volatile memory, downscaling feature of Ic at sustained thermal scalability makes STT-MRAM a promising candidate towards sub-20-nm node non-volatile memory.
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About the authors
Woojin Kim, senior engineer of SEC (Samsung Electronics Company) R&D center, joined the MTJ process development team in 2007. He received a Ph.D. degree in materials science and engineering from POSTECH in 2007. He has initiated and designed MTJ structure and integration process.
Younghyun Kim, senior engineer of SEC R&D center, joined the MTJ process development team in 2008. He received a Ph.D. degree in materials science and engineering from the University of Pennsylvania in 2007. He focused on pulse IV measurement and integration process.
J. H. Jeong, senior engineer of SEC R&D center, joined the MTJ process development team in 2005. He received his master’s degree in materials science and engineering from Yeonsei University in 2005. His major is circuit design and integration process.
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