Shrinking geometries and efficient design techniques are helping to reduce die sizes, which lowers the cost of semiconductor devices. Despite these improvements, increased competition and smaller gross margins are forcing semiconductor companies to reduce the overall cost of IC production even more. One of the major contributors to total device cost is the cost of testing.
For the digital portion of ICs, DFT (design for test) techniques have significantly reduced test complexity and test times. Unfortunately, testing the analog portion of an IC is much more complex. As a result, most engineers still perform analog measurements using conventional methods, such as bringing the analog output to a package-level pin and performing the measurement using external instruments. This approach has its disadvantages, especially in terms of time and cost.
Fortunately, there is a way to reduce the test time spent on clock frequency measurements. By performing on-chip frequency measurements, device manufacturers can reduce their dependency on external instruments and can perform concurrent, parallel, and faster frequency measurements without adding any significant silicon area. In fact, one study has shown a reduction in test time of more than 50%. For devices with many clock sources, this can lead to significant test cost savings.
Follow the jump directly to the article on EDN.. The article covers test challenges for ICs and a new DFT technique.