# Multichannel DDS enables efficient FSK/PSK modulation

Frequency-shift keying (FSK) and phase-shift keying (PSK) modulation schemes are used in digital communications, radar, RFID, and numerous other applications. The simplest form of FSK uses two discrete frequencies to transmit binary information, with Logic 1 representing the mark frequency and Logic 0 representing the space frequency. The simplest form of PSK is binary (BPSK), which uses two phases separated by 180°. Figure 1 illustrates the two types of modulation.

Figure 1. Binary FSK (a) and PSK (b) modulation.

The modulated output of a direct digital synthesizer (DDS) can switch frequency and/or phase in a phase-continuous or phase-coherent manner, as shown in Figure 1 (also see Ref. 1), making DDS technology well suited for both FSK and PSK modulation.

This article describes how two synchronized DDS channels can implement a zero-crossing FSK or PSK modulator. Here, the __AD9958__ two-channel, 500-MSPS DDS is used to switch frequencies or phases at the zero-crossing point, but any two-channel synchronized solution should be capable of accomplishing this function. In phase-coherent radar systems, zero-crossing switching reduces the amount post processing needed for signature recognition of the target; and implementing PSK at the zero crossing reduces spectral splatter.

Although both of the DDS-channel outputs are independent, they share an internal system clock and reside on a single piece of silicon, so they should provide more reliable channel-to-channel tracking over temperature and power-supply deviations than the outputs of multiple, single-channel devices synchronized together. The process variability that may exist between distinct devices is also larger than any process variability you might see between two channels fabricated in a single piece of silicon, making a multichannel DDS preferable for use as a zero-crossing FSK or PSK modulator.

Figure 2. Setup for zero-crossing FSK or PSK modulator.

A critical element of any DDS is the phase accumulator, which, in this implementation, is 32 bits wide. When the accumulator overflows, it retains any excess value. When the accumulator overflows with no remainder (see Figure 3), the output is precisely at phase 0, and the DDS engine starts over from where it was at time 0. The rate at which the zero-overflow is experienced is referred to as the grand-repetition rate (GRR) of the DDS.

Figure 3. Basic DDS with overflowing accumulator.

The GRR is determined by the rightmost nonzero bit of the DDS frequency tuning word (FTW), as established by the following equation:

GRR = FS/2n,

where FS is the sampling frequency of the DDS, and n is the rightmost nonzero bit of the FTW. For example, suppose a DDS with a 1-GHz sampling frequency employs 32-bit mark and space FTWs with the binary values shown. In this case, the rightmost nonzero bit of either FTW is the 19th bit, so GRR = 1 GHz/219, or approximately 1907 Hz.