though stage-based OCV is an improvement over a fixed OCV there are
simple ways to get even better results. These methods include.
Use both clock and data stage-based OCV tables
- Use both clock and data stage-based OCV tables
- Apply design rules to limit load and slew ranges
- Use design specific information to limit load and slew ranges
our testing using both clock and data path OCV tables improved timing
results significantly. Our test design was a synthesized ARM core
running at 1Ghz using a TSMC 40nm library.
Limiting analysis to
clock only gave mixed results – with some paths improving and others
getting worse. However, once both clock and data derates were applied
timing results improved significantly.
Applying design rules in table generation
derate maps show that some cells worst derate may come from an area
outside what would be considered the “normal” operating range of the
cell. For example, many cells’ default derate value comes from the
extremes of the combinations characterized load/slew points.
Figure 5: Index files help apply design limits to derate tables
are often characterized for load and slew ranges much larger than the
expected operating region. By applying design rules the effective area
of the derate calculation can be reduced.
AOCV FX™ reads TSMC’s index file format which allows detailed selection of load and slew ranges for each cell.
Design specific table generation
mining data directly from static timing analysis you can find the range
of load and slew values that a cell typically encounters. We make it
easy to export this data from your STA tool with a simple Tcl script.
Figure 6 shows a derate map timing data overlaid. Each x represents the
load and slew value for an instance of the cell as seen during timing
Figure 6: Using design specific data can produce pessimistic derates
combining the load and slew ranges found in timing with the variation
database we are able to very quickly regenerate stage-based OCV derate
tables that eliminate the pessimism of the worst case value found at the
extreme load/slew combination.
Each design can now have a
unique set of derate tables by mining the timing information specific to
that design. In this way, different designs are not penalized by the
worst-case behavior in the library or by the behavior of the cell in
different designs. Because the original simulation was saved in a
database regenerating tables for each design or after an ECO is very
The results of adding design specific rules and load/slew
ranges to our test case are shown in the table below. The improvements
Other uses for the variation database
addition to generating stage-based OCV tables, a variation database
provides the opportunity to use variation to make additional refinements
in the design process and create more robust designs. All of the
simulation data including delays, variation measurements, conditions
such as voltage and temperature can easily be queried from the tool or
exported to external files as raw text or an SQL database making it
possible to add your own variation checks or do fast “what if” analysis.
Figure 7: Using the variation database and timing data together leads to interesting new applications
example, we’ve used the data in the variation database to identify
outlier cells in a design where variation was high. These cells are
targets for optimization or design refactoring in order to drive them in
to a more reasonable load and slew range or their “sweet spot” in terms
of variability. In addition, by eliminating these cells all of the
other cells benefit by getting a smaller derate factor.
Further analysis can identify critical paths where variation is high and may require closer inspection before tape-out.
Validating results with statistical path analysis
new derating techniques need to be verified in order to be considered
safe for general use. Statistical timing analysis is a useful way to
validate AOCV derates. A correct derating strategy should not produce
results that are more optimistic than statistical analysis.
analysis used Path FX™, a fast, path-based, statistical timing tool that
is much faster than Monte Carlo SPICE. By using a fast statistical
timing analysis we were able to validate thousands of paths and compare
the results against our AOCV timing results.
We were pleased to
see that applying these techniques stayed within the boundaries defined
by full statistical analysis. In addition, it shows that while these
techniques are good there’s still plenty of opportunity for continued
stage-based OCV provides material improvements to timing margin over a
fixed global OCV derate; worst case stage-based OCV derates can still be
overly pessimistic – penalizing designs for variance outside their
operating region. Stage-based derates can be improved significantly by
combining variation information with design specific timing results. In
addition, combining this information allows designers and EDA vendors to
make additional refinements in the design process and help create more
Dunsmoor is Director of Product Management for CLK Design Automation.
As one of the company's first employees, Ahran has helped CLK DA develop
new categories of physical design and variation analysis tools. Ahran
has over 15 years of EDA industry experience with a background in
verification, static timing, and information visualization.
Dr. João Geada
Geada has over 20 years of EDA experience. Dr. Geada leads the
development of CLK DA’s timing and advanced on chip variation products.
He is the author numerous papers and patents around static timing
analysis and signal integrity.
Previously, Dr. Geada was one of the
lead architects in the verification and simulation group at Synopsys.
Prior to Synopsys, Dr. Geada was a senior researcher at Cadence Design
Systems and started his career at the IBM TJ Watson Research Center. Dr.
Geada holds a PhD and Bachelor degree in Engineering from the
University of Newcastle on Tyne (UK).
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