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Accelerate partial reconfiguration with a 100% hardware solution

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DrFPGA
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re: Accelerate partial reconfiguration with a 100% hardware solution
DrFPGA   5/28/2012 4:59:39 PM
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Seems to me that the tools have a long way to go to make dynamic reconfiguration something that most designs will be able to do. For example, the need to have the decoupling logic explicitly defined (if I'm reading the article correctly) is the type of thing I would expect to be handled automatically.

angelmc
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re: Accelerate partial reconfiguration with a 100% hardware solution
angelmc   6/20/2012 9:27:29 AM
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In the university we worked (and they still do) on a similar approach for partial reconfiguration through the ICAP but that was handeled entirely by the FPGA itself. The maximum clock frequency for the ICAP was achieved with little FPGA resources consumption.

angelmc
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re: Accelerate partial reconfiguration with a 100% hardware solution
angelmc   6/20/2012 9:56:40 AM
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Just a clarification: they still work with the reconfiguration engine (as they call it) that works correctly. They are working with upper layers to optimize full applications.

srikanth1986
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re: Accelerate partial reconfiguration with a 100% hardware solution
srikanth1986   2/14/2013 11:26:31 AM
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I had realized a 100% hw solution for PR way back in 2010. So I don't know whats so innovative about it now.

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