The inexorable demand for electronic systems with increasing bandwidth and decreasing size puts more high-speed channels in ever-closer proximity. Technologies such as 40-Gbps and 100-Gbps Ethernet employ up to 10 channels at 10 Gbps each or four channels at 25 Gbps. When so many high-speed serial lanes reside in a single system, they're bound to interfere with each other.
Serial buses such as Ethernet, Fibre Channel, and PCI Express capitalize on the robust nature of serial technology, with its interference-canceling differential signaling and jitter-canceling embedded clocking. To achieve their data rates, these buses employ multiple serial lanes that operate in parallel. With each additional lane, a bus scales to a higher data rate (Ref. 1).
Unfortunately, every lane is both an aggressor and a victim. Differential signaling can only partially cancel crosstalk at these high data rates. After a decade spent developing serial data technologies and dealing with jitter, closed-eye diagrams, and pre-emphasis and de-emphasis, and then having equalization improve signal quality and reduce bit errors, engineers have realized that crosstalk has come back to haunt them.
Marty Miller, chief scientist at LeCroy, put it like this: "When we started switching from parallel to serial interconnects, crosstalk stopped being a big concern, but now we're moving to serial channels in parallel. We have systems with dozens of SerDes on one chip operating at 50 times the data rate [of parallel buses]. We're looking at a crosstalk nightmare."
The problem of cross talk is alleviated in the cables by using shielded ones (for Copper) so the problem is more acute in the mother boards and connectors in high speed serial communication. The problem in mother boards has always been around and designers dealt with it by the choice of materials and design parameters. It is getting tougher on the backplanes and motherboards to route signal traces in tens of serial links no doubt!
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.