the hierarchical and flat approaches are at their limits as design
sizes grow beyond the 100 million instance mark. To effectively handle
these designs without sacrificing performance, power, area, or
time-to-results, a hybrid flow, otherwise known as the pseudo-flat
approach is a great alternative. The idea here is to break down the
design into blocks just as in the hierarchical approach and spawn those
blocks off for implementation. However, unlike in a hierarchical flow,
once the pre-CTS optimization is completed at the block level, the
blocks are then merged at the top level and the boundaries removed to
optimize the design flat across the entire chip.
flattening or preserving blocks based on timing criticality or other IP
related issues allows more flexibility to the designer. At this point,
the design can proceed through the rest of the flow following the
traditional flat approach. Most of the heavy lifting in the design flow
is during the pre-CTS step, which is done in a hierarchical style. But
to retain the full benefit of top-level design timing/area/power closure
from the flat approach, the design is finalized in a flat design style.
Figure 3 shows a design view of a pseudo-flat flow.
3. A view of a design in a hybrid, pseudo-flat flow. The design is
treated hierarchically until pre-CTS optimization is complete for all
blocks, then the blocks are assembled and flattened as needed for the
rest of the implementation.
The pseudo-flat flow combines
the benefits of the flat and the hierarchical flows, providing good
performance and design utilization and fast turnaround times. It also
eliminates the inter-block timing modeling inaccuracies associated with
the hierarchical flows and results in the most timing- and
power-efficient clock trees.
From a design planning perspective,
to successfully support the pseudo-flat flow, the physical design tools
need to have the capacity to handle top-level optimization of these huge
designs and a compact datamodel to minimize the memory footprints
discussed earlier, considering clock early during the design planning is
critical for fast design convergence, so the tools need to support
clock planning as part of the design planning step. Achieving a good
macro placement is also critical for extracting the best performance of
the design and it should be based on data flow and connectivity analysis
It is clear that IC design sizes are going to explode as we
march down the process nodes, regardless of the end application. For
designers to effectively tackle the design size problem, innovative
solutions like the pseudo-flat flow will become an essential strategy.
1. Mentor Graphics whitepaper, “Advanced Floorplanning with Olympus-SoC
” describes a mixed-hierarchy, or pseudo-flat flow, for floorplanning, macro placement, and pin assignment.
About the author
Inness is a place and route specialist at Mentor Graphics, where he
applies his 20 years of experience to tool and methodology development
for the most advanced designs. Andy received his BSEE from Iowa State
University and MSEE from Southern Methodist University.
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