The PLL synthesizer has an advantage in flexibility. There are two types of PLLs, and selecting between the two involves making the correct tradeoff between flexibility and performance. An integer-N PLL offers the best jitter performance and can address all of today’s jitter requirements except the most stringent. Integer-N PLLs are optimized to output a frequency Fout = N x Fin where N is an integer. There are advanced multi-phase architectures that allow Fout = N/8 x Fin, making the input/output relationship more granular. There is, however, a limit to the granularity of the frequency multiplication factor.
The most flexible PLL contains a modulator in the feedback path that enables it to output any frequency while being locked to an arbitrary input frequency. This topology is commonly referred to as fractional-N and generates an output Fout = N*M x Fin where the M can be a very long decimal, on the order of 1 PPB of N. Because the modulator is in the feedback path and feeds the phase detector, the noise it creates appears as input referenced noise. This noise goes through the PLL and is filtered by the loop bandwidth. High-frequency modulator noise is attenuated, but, low-frequency mixing noise cannot be filtered by the loop and shows up at the output. The flexibility that the fractional modulator brings comes with a penalty to phase noise performance.
Although some high-data-rate applications can tolerate the added jitter induced by the modulator, others such as 10/40/100 Gigabit Ethernet that require 150 fs to 250 fs rms phase jitter integrated from 12 kHz to 20 MHz cannot use fractional-N PLLs. Managing the input to output frequency limitation of integer-N is a necessary tradeoff when striving for sub-250-fs performance. Applications such as wireless base stations that require sub-100-fs performance have to tradeoff additional flexibility by only employing AFM technology.
As communication systems become ever more complex, more ICs require clock inputs. As these systems get faster, these ICs require faster and more precise clocks. Designers will either need to use additional PLLs, or they will find themselves required to use precision fan-out buffers to distribute and duplicate a very high performance clock without adding much jitter.
There are several different ways to build an IC input or output stage capable of sending clean high-speed signals down a transmission line. The different types of input/output structures have different loading requirements, produce different signal amplitudes and offsets, and therefore are defined by different standards. Each of these technologies comes with its own advantages and disadvantages.
For clocking, it is preferable to choose a signaling standard that features a large amplitude and a fast edge rate. Clocks are purely AC signals and AC-coupling is recommended for optimal performance. With AC-coupling, DC offset does not matter because the signal is re-biased at the receiver. The amplitude matters because at high frequencies, transmission lines attenuate the amplitude of the signal. In large systems, transmission lines can get fairly long and at times, the clock signal will be strongly attenuated resulting in distortion at the receiver. Additionally, higher-order harmonics are filtered out by the transmission line and the signal becomes a sine wave. A larger amplitude sine wave will have steeper edges resulting in less jitter at the crossing point where there is most susceptibility to jitter.
When designing a clock tree, it is important to consider the total jitter at the output. Deterministic jitter adds up linearly, but clock jitter is a random quantity with a Guassian distribution. Therefore, rms addition must be used to add up the total random clock jitter:
We use rms addition to get the total jitter at the output of the clock tree:
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