With the plethora of mobile and consumer applications redefining the requirements for designing chips for low power requirements, designers have to be aware of power intent formats like Si2’s CPF (Common Power Format) and Accellera’s IEEE1801 UPF (Unified Power Format) to define and capture power intent for design implementation and verification. Designing and analyzing low power management in chip designs can best be accomplished at RTL, where designers adopt these formats to implement low power strategies like voltage and power islands. In this article, we will discuss several approaches on how these formats play a key role in capturing power intent for RTL design analysis and verification.
Power-intent aware CDC analysis
Clock domain crossing (CDC) verification ensures that proper synchronization has been done for all asynchronous clock crossings in the design. Else, these crossings can cause metastability in the design and can lead to functional failure in the chip. Typically, exhaustive CDC verification is done at the RTL stage and handed off to design implementation. As part of low power implementation, isolation logic is inserted by synthesis tools at the gate level to isolate the power domain outputs when the domain is powered off. Isolation logic is used to ensure that unknown signals do not propagate to downstream logic and cause electrical problems.
This isolation logic insertion at the gate level may now lead to un-synchronized crossings. Figure 1 illustrates the problem. In this circuit, there is power domain crossing from a switched off domain PD to an always-on domain VD, where the crossing between S and D registers are synchronous. Hence, there is no CDC issue with this circuit.
The power intent has been described in UPF to capture the domain information as well as the isolation strategy such that the synthesis tool can insert the isolation cell to isolate the PD output signal to a known value during the power shut down. However, due to the isolation logic insertion, a new logic path has been created, which in fact is a clock domain crossing (C2->C1, C1, C2 are asynchronous clocks). This crossing requires additional synchronization, which was not done at the RTL stage. Detecting such crossings is only possible by analyzing the RTL with power intent awareness. Otherwise, they may be detected late in the design process, which causes painful surprises or even chip failures. Based on the complexity of changes involved, re-iteration of Synthesis/P&R is needed, which can adversely impact design schedules.
Figure 1: Isolation logic insertion at gate level causing metastability issues