Engineers have been striving for the past few decades to decrease the size of electronic systems as well as increase flexibility. With the advent of reprogrammable FPGAs, systems could be made that were less expensive and could be upgraded on the fly. This article discusses on how to configure FPGA-based systems over USB to implement the flexibility of in-field upgrades. This method can also serve to replace the popular JTAG configuration interface and eliminate the need for a separate JTAG connector on the board, hence reducing cost and board space.
Field Programmable Gate Arrays (FPGA) are simple programmable logic blocks with a massive fabric of electrically programmable interconnects between the logic blocks. An FPGA enables users to configure the logic blocks and the interconnections between the logic blocks. FPGAs were introduced to implement the entire functionality of a system on one chip and provide flexibility of reprogramming. Today, FPGAs cover a broad market of applications such as automotive, industrial, medical, consumer electronics networking, security, high performance computing, video and imaging, digital signal processing, etc. We will see the various types of FPGA configuration in the below sections.
FPGAs work in two modes: configuration mode and user mode. On power up, the FPGA enters the configuration mode for programming. Configuring a FPGA means sending a bit stream of ‘0’ and ‘1’ into the device through special pins. Once the FPGA is configured, it switches into user mode to perform the programmed logic function.
Most FPGAs use SRAM to store configuration data. Since SRAM is a volatile configuration, the configuration data needs to be downloaded to the SRAM upon power up. These configurations can also be automatically loaded from non-volatile memories like PROM, SPI Flash, or an external processor chip. Microprocessors, microcontrollers and digital signal processors can also download the configuration data to the FPGA's SRAM. Apart from these methods, the configuration can be also be downloaded via the most popular JTAG interfaces, USB interfaces, etc.
Types of FPGA Configuration
Configuration of an FPGA can be performed by either placing the FPGA in master mode or slave mode. In Master mode, the FPGA generates the configuration clock and controls the configuration data. In this mode, the FPGA generally downloads the configuration bit stream from non-volatile memories like SPI, Flash, and PROM. When using a SPI Flash, the FPGA acts as a SPI master where the configuration is downloaded from this SPI Flash as shown in Figure 1A. In Figure 1B and Figure 1C, the FPGA downloads the configuration data from PROM. Although non-volatile memory like PROM can be internal or external, it is usually external to the FPGA.
In this slave mode, the FPGA can be configured using external intelligent devices like microcontrollers, microprocessors, digital signal processors, etc. or using a JTAG or USB interface.
The three most commonly used methods smart devices like microcontroller, microprocessor, and DSPs use to load configuration data are synchronous serial, SPI slave, and parallel modes.
Synchronous serial interface
Usually two lines – data and clock – are used to download the configuration in this method. On the rising-edge of the configuration clock, the configuration data bits are shifted into the FPGA.
SPI slave mode
Here the FPGA acts as an SPI slave and an external microprocessor, microcontroller or DSP acts as the SPI master. The processor or the controller loads the configuration bit stream data from an off-chip memory source using the SPI lines.
Parallel Mode (8, 16 or 32 bit)
Most FPGAs have the option of 8/16/32-bit selection when configuration data are sent in parallel. This method is one of the fastest modes of loading the configuration data.
Configuration Using the JTAG Interface:
The JTAG interface is a four/ five pin serial interface. The five pins are TDI (Test Data In), TDO (Test Data Out), TCK (Test Clock), TMS (Test Mode Select), and TRST (Test Reset). The TRST pin is optional. JTAG is commonly used for hardware debugging and boundary scan testing. This interface can also be used for configuration programming. Figure 5 shows the configuration signal mapping using the JTAG interface.
Configuring an FPGA Over a USB Interface
A high-speed USB interface can be integrated into an FPGA-based solution in the following ways:
- USB protocol stack intellectual property (IP) with an external transceiver: In this method, the SIE IP is implemented within the FPGA or ASIC and used along with an external transceiver. This method offers the advantage that the hardware required is minimal. However, development of USB Stack IP will consume valuable time as well as engineering resources. On the other hand, the use of a third-party IP can prove costly. The implementation of the higher-level protocol and application functions also take up a significant amount of valuable FPGA resources.
USB Bridge IC with integrated SIE and transceiver: This technique interfaces an external serial interface engine as well as a transceiver to the FPGA. Signal-level protocol management is no longer handled within the FPGA. There are some savings here with respect to FPGA resources. However, higher-level USB protocol implementation is still done within the FPGA. In this case, a decision would have to be arrived at by analyzing the cost of the external hardware required compared to the amount of FPGA resources saved.
Controller + FPGA: This method interfaces the FPGA or ASIC to an intelligent USB controller IC that would take care of all the USB protocol level management. Controllers can offer the flexibility of a configurable number of endpoints, FIFO size, and may even contain a microcontroller to handle high-level USB protocol management. Such peripheral controllers may also contain the capability to handle some application-level functions, thus freeing the FPGA or ASIC from the need to perform them.