critical nets on higher metal layers to meet timing is not a new
concept. There are several approaches in use today; however, most are
iterative and can be error prone and time consuming.
Layer usage control
this approach, the least resistive upper metal layers are ignored
during pre-route and made available only at post-route. The intent is to
control upper-layer utilization and prevent routing of non-critical
signals on these layers. However, with upper layers completely blocked
during pre-route, and the predominant use of highly resistive lower
layers, it can lead to over-buffering of critical nets.
Using soft non default rules (NDR)
spacing rules can be used to manipulate the parasitics of critical nets
through width and spacing constraints. An iterative, design dependent
approach, it requires several trial place and route runs to determine
the optimal spacing length thresholds and spacing weights to assign to
approach is the use of scaling factors to control the average R used
for pre-route estimation – long nets get scaled to lower R and short
nets to higher R, thereby improving the overall interconnect
performance. Determining scaling factors is an iterative process
relying heavily on the expertise of the user. Furthermore, it requires
careful analysis as it can quite easily impact pre-route optimization
priorities. Parasitic scaling is a viable option for advanced users,
but can be overwhelming for those unfamiliar with this technology.
Global route-based pre-route estimation
approach involves global routing nets during pre-route. While it
eliminates the inaccuracies of averaging R during pre-route, it can be
over-engineering for non-critical / short nets. The ideal solution to
strike the right balance between QoR and runtime is to have just the
critical / long nets globally routed.
Automatic layer-aware pre-route optimization – The smarter approach
At 28nm, there is a need for a more intelligent and automated approach to layer-aware optimization.
Figure 6: Layer optimization methodology
An optimal solution should work within the existing place and route
flow, as well as provide flexibility for layer promotion at every
implementation stage. Figure 6 details such a methodology, which should
consist of three steps: prevention; refinement; and preservation.
- Prevention requires critical net identification and layer
assignment during pre-route. Physical and timing properties such as net
length, fanout and slack can be used for critical net identification.
Flexibility in net pattern selection may be required for designs that
are macro-dominated or data-path intensive, or for those with
rectilinear floorplans. In such cases, attributes such as congestion,
connectivity and aspect ratio can be used to refine net selection.
- An optional refinement step can be done post optimization to
opportunistically reroute selected buffer trees to the upper layers. It
may be needed to further tune quality of results (QoR) for
timing-critical designs. Finally, the preservation of layer assignment
through detail route helps complete the solution.
A phased approach such as the one explained above will result in
effective buffer reduction and improved performance. Advanced
capabilities such as improved critical net selection and continuous
layer assignment evaluation will enable wider adoption of this
Figure 7: Critical net selection process for layer assignment
layer-aware pre-route optimization in IC Compiler adopts a similar
approach and is available today. Early results from several customer
designs show improvements in clock frequency and buffer count reduction
(see Figure 8).
Figure 8: Results from automatic layer-aware pre-route optimization in IC compiler
advanced technologies, designs can no longer afford buffering and driver
upsizing as their only techniques to manage interconnect delays.
Accurate parasitic estimation of interconnects earlier in the
implementation flow has become necessary to minimize design costs and
meet design QoR. At 28nm, the dramatic resistance variation seen across
metal routing layers provides both challenges and opportunities for
accurate pre-route parasitic estimation. While there are several
approaches in use today that leverage this resistance variation, an
intelligent and automated solution is needed to address existing
limitations and provide a more robust flow. With its Automated
Layer-Aware Optimization technology, IC Compiler provides a more
holistic approach to pre-route parasitic estimation, thereby enabling
better performance prediction.
About the author
Rangarajan is a technical marketing manager for IC Compiler at
Synopsys. She has over 15 years of experience in the ASIC and
semiconductor industry. Prior to Synopsys, she worked at LSI as an ASIC
design engineer focusing on place and route, design for test and static
timing analysis for several key customer designs. Before that, she
worked at Texas Instruments on the library characterization team.
Rangarajan has a bachelor of engineering degree in electronics and
communication engineering from the Government College of Technology in
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