Today’s boards look more like integrated circuits (IC), so we are starting to see a correlation between problems seen in chip test and those seen in board test. What’s the best way forward?
Testing electronic circuits has been an important topic in the industry since the first transistor was developed, and today it is as relevant as ever. Test strategies are graded by how close they come to the ideal test solution, which doesn’t add any cost to the product under test during design or production. Most of us agree that product testing is absolutely necessary, as part of design validation, as a quality indicator for manufacturing process control, or for the detection of defective products prior to shipping them to a customer. However, we do have certain requirements that should be met by our test solutions: test development and execution should be fully automated and should be done in essentially no time; test equipment should be very inexpensive; fault coverage should be 100%. Industry trends give cause for concern, though, considering cost of test can be a significant part of the overall development and manufacturing cost.
Adding to these challenges is the complexity of today’s high-speed designs, and the lack of available test access on many of today’s printed circuit board assemblies (PCBAs) or boards. The combined forces of these characteristics result in systematic changes in the balance of product design and product test. In fact, we are starting to see a correlation between problems seen in chip test and those seen in board test (see Figure 1).
Figure 1: Chip and board structures seem to be on a path of convergence when considering their electrical and physical characteristics
Today’s boards look more like integrated circuits (IC) due to the loss of access to internal circuit nodes, and the rapid development of three-dimensional (3D) ICs with multi-die integration results in structures that are similar to boards and systems. In fact, the 3D board with very little physical access seems to be looming on the horizon. Simultaneously, the combination of new packaging and integration technologies has resulted in historic levels of complexity. While several years ago multiple boards were necessary to create complete system designs, today some such systems can be realized in system-in-package (SIP) or even system-on chip (SOC) designs. As a result, board size can be minimized and new possibilities are available to create super-complex systems. No matter how a design is arranged, however, from the perspective of test engineering the fundamental questions are: How can such highly complex systems be tested appropriately and efficiently, and how can designers take advantage of any synergies between chip test and board test approaches?
The saga of non-invasive test access
“Divide and conquer” is a proven battle strategy that is also well suited for the test arena. Partitioning circuit structures into testable elements is a prerequisite for a successful test strategy. This is one of the reasons why in-circuit test (ICT) became so successful for board level tests. However, ICT’s disadvantage is that it approaches circuit test structurally and tests components individually. Unfortunately, this requires invasive test access which is now becoming extremely challenging for modern boards. The good news is that these test access problems were predictable, and, in 1990, IEEE Std 1149.1 was developed by the Joint Test Action Group (JTAG) to address them. This standard moves the so-called pin-electronics of a tester into the unit under test (UUT) in order to enable non-invasive test access without ‘bed-of-nail’ adapters. The design-integrated pin-electronics is controlled through the JTAG test bus. This test bus needs to be incorporated into the UUT by the board designer, providing test access available implicitly rather than as an afterthought.
The brilliance of IEEE Std 1149.1 is the open expandability of its register architecture combined with the universal test bus interface (Test Access Port, TAP) and its protocol definition. These properties allowed IEEE Std 1149.1 to become the base technology for new non-intrusive methodologies and standards for testing, debugging, programming, and emulation. As a result, the portfolio of test access strategies at the board level has definitively changed.
Today we can differentiate three principle classes of access strategies (see Figure 2):
• Native connector access (access through design integrated I/O interfaces)
• Intrusive board access (access through physical test nails and probes)
• Embedded system access (ESA; access through design integrated test bus)
Figure 2: Classification of electrical test access strategies at board level.
While these classes are not mutually exclusive in their practical usage, the applicability of an actual combination of these access strategies depends on the individual capabilities of the chosen automated test equipment (ATE) platform. So, how do these access strategies relate to each other and what does ESA mean in a practical sense?Continue reading pages 2-4 of this article on EDN