This article originally appeared in Linear Audio Volume 2, September 2011. Linear Audio, a book-size printed tech audio resource, is published half-yearly by Jan Didden.
Power amplifier design is a topic which finds wide interest in the audio community - not only in the sense of commercial concerns, but also as a fascinating and often demanding challenge for electrical engineers and do-it-yourself enthusiasts. The trade-offs involved are numerous; from the basic requirements for accurate audio signal reproduction (such as good frequency response, low noise and distortion, etc.) over contemplations regarding efficiency, safety and complexity to constraints as a result of current fashion,which might favour certain design techniques for no particular objective reason.
As there will never be a solution which simultaneously fulfills all demands, we can expect an ongoing development in this field and I hope to add to the state of the art with the humble contribution of this article.
Most audio power amplifiers have been built around topologies with two gain stages; the first gain stage forms a transconductance stage (i.e. a voltage-to-current converter, typically implemented by a simple differential pair), and the second a transimpedance stage (i.e. a current-to-voltage converter, usually a common-emitter transistor configuration) which also provides Miller compensation.
A full audio power amplifier capable of driving a speaker load is completed by the addition of a unity gain power output stage, e.g. a complementary Darlington emitter follower.1
As explained by Self  in great detail this configuration is very suitable to build discrete power amplifiers, as it offers potentially excellent performance at low complexity.
There are amplifier topologies which use three gain stages; however proper compensation is usually difficult to achieve, and the possible performance improvement is often benign compared to the increase in complexity. On the other hand, it is also possible to build amplifiers with just one gain stage. Unfortunately they require a power output stage with very high and constant input impedance for reasonable distortion performance; furthermore typical topologies show rather high sensitivity to transistor and resistor mismatch. This makes them less suitable for discrete implementation and the required complexity for a given performance goal will often be higher than with the use of a two stage topology.
In this article I will consider - once more - the two-stage topology. Before I present the new amplifier architecture in section 3, I'll first discuss typical prior-art topologies and some of their shortcomings in section 2.
Later in this text (sections 4–7) detailed advice for the optimum practical realisation of the novel amplifier topology is given. Section 8 considers several possible adaptations and alterations of the presented circuit, while in section 9 I show experimental verifications of the new amplifier concept. This article is finished with a brief conclusion, and an appendix covering noise sources in folded cascode stages.
I should add that some authors count the output buffer as explicit gain stage, so the standard amplifier topology is then referred to as three-stage amplifier. Personally I prefer the other nomenclature which is in line with the large IC operational amplifier literature, and which appreciates that for the basic conceptional functionality of amplifiers the output stage is not strictly necessary.
2. Review of Typical Two-Stage Topologies
Figure 1 depicts a conceptual schematic of what is generally accepted to be the standard two-stage amplifier topology. Q1 and Q2, together with the current source I1, form a differential pair which is loaded by a Widlar current mirror (Q3 and Q4). These parts make up the first stage; as noted above it is a transconductance gain stage.
Figure 1: Conceptual schematic of the standard two-stage amplifier topology.
The second gain stage with transimpedance behaviour is formed by Q5, Q6 and I2. C1 is the Miller compensation capacitor; it defines, together with the transconductance of the first stage, amplifier open-loop gain at high frequencies and hence stability margins [1,2,3]. Towards high frequencies the compensation capacitor transfers global loop gain to local second stage feedback.
This feedback reference voltage connection of the Miller compensation loop creates several problems. One of these is a reduction in power supply rejection; as the base of Q5 is referenced to the negative supply by the base-emitter junctions of Q5 and Q6, the ripple of the negative power supply rail voltage is superposed to the intended output signal. This effect is reduced by the global feedback loop. The rail injection hence increases towards high frequencies,where less global feedback is available to suppress the effect.
In other words, available amplifier loop gain sets an upper limit to power supply rejection; with standard Miller compensation power supply rejection decreases at 20 dB per decade, and becomes 0 dB at the unity loop gain frequency. With a unity loop gain frequency of 700 kHz, which can be considered a typical figure for audio power amplifiers, power supply rejection is hence limited to about 30 dB at 20 kHz.2 This estimate ignores second-order effects which depend on the exact implementation, but the result is still useful and valid for a rough analysis. Note that for the positive power supply there is no such primary injection path; the power supply rejection will be largely independent of frequency, and thus is usually much less critical.
Power supplies of power amplifiers are typically unregulated for efficiency reasons [1,2]. This means that they carry substantial ripple related both to the mains frequency and harmonics of the output signal; it is highly undesirable that this ripple content be superposed to the audio signal.
Yet it is difficult to give exact figures for the needed power supply rejection, as this depends on the expected performance level, output power and power supply design details. However it is unlikely that the above quoted figure of 30 dB at 20 kHz is sufficient for any quality power amplifier. Also note that ripple related to the harmonics of the output signal extends well above the audio frequency range; hence the region of high power supply rejection should reach at least up to 100 kHz.
To improve the power supply rejection of the basic two-stage topology from figure 1, several solutions have been presented in the literature. The simplest one uses a RC low pass filter, inserted between power output stage and transimpedance stage, to reduce the ripple content on the power supply before it feeds the transimpedance stage.
To be appreciably effective, the low pass filter requires a rather large time constant. If the capacitor shall not become unreasonably large, the resistor must have a sufficiently high value. The inevitable DC voltage drop across this resistor will reduce maximum output voltage swing in many cases. This is further exacerbated by the fact that Q6 will need, in a practical implementation, an emitter resistor for current limiting. This further reduces available output voltage swing.
To avoid this issue, a separate additional negative power supply for the small-signal stages has been used [1,2]. This supply is, for example, derived from an additional mains transformer secondary winding and has rather low current requirements; hence it can easily be arranged to have both sufficient voltage and very low ripple.While the cost of such a solution is modest (at least in the context of a commercial design where a custom power transformer is usually specified anyway), it remains a rather inelegant brute force solution.
Conceptually more pleasing is the use of Ahuja compensation [1,4]. By means of a cascode the input node of the transimpedance stage is referenced to ground rather than a power supply rail. This removes the basic power supply injection route, however in many cases second-order effects make this arrangement less effective than the previously discussed means. Furthermore certain implementations can suffer from local instability of the Miller compensation loop (which now includes at least one additional transistor), or may contribute significantly to the voltage noise of the amplifier.
2 Note that this figure is related to the output, not the input, of the amplifier. This is unlike the figures quoted in operational amplifier data sheets. Figures related to the output show a value which is lower by the noise gain of the used amplifier configuration - typically 20–30 dB for audio power amplifiers.
Slew rate in the two-stage topology
The last difficulty of the two-stage topology shown in figure 1 which I'll discuss here is related to slew rate. While the output of the second stage can sink very high currents by turning on Q6, current sourcing is limited by I2. This can lead to a slew rate limitation, particularly as under transient conditions the output current of I2 may be reduced by junction capacitances , and if the output stage demands high drive currents.
I have presented a solution to this in , but there are some limits to its effectiveness. Of course it is very arguable whether there are any audible artefacts from such slew rate limitations within a well designed amplifier . Nonetheless, at least from a marketing point of view, it is desirable to tackle this issue.
To make the sourcing and sinking output current capabilities of the second stage equal, and as a first-order approximation unlimited, many prior art amplifiers have implemented a push-pull arrangement similar to that shown in figure 2. To derive the complementary drive signals required for the transimpedance stage formed by Q9–Q12, two complementary differential pairs (Q1–Q4) are employed. Not shown in the schematic diagram is the bias current control necessary for the second stage; some solutions for this are presented in [2,5,7,8].
Figure 2: Basic two-stage amplifier with push-pull transimpedance stage. Necessary bias control circuit for the second stage is omitted.
While this amplifier topology, with some minor modifications of the input stage, easily supports very high slew rates (see e.g., ), it does not fully solve the power supply rejection issue discussed above. Due to the complementary nature of the topology both power supply rails now act as main injection route. However, as is easily shown by simulation or other forms of sufficiently detailed theoretical analysis, the injection from the negative power supply rail is reduced by 6 dB compared to the amplifier from figure 1 for a given amount of loop gain.
Furthermore ripple signals which are present in a complementary form on both power supply rails are theoretically rejected. But this rejection mechanism is not particularly reliable, as it depends, e.g., on the matching of the smoothing capacitors employed in the positive and negative power supply rail. So this amplifier architecture has again to rely on either RC filtering, additional power supplies for the small-signal stages or Ahuja compensation for excellent power supply rejection.
Further minor problems with this topology arise from gain mismatch in the two complementary halves.3 This can lead - according to simulation results - to both additional distortion and instability, although at least the latter is easily fixed by connecting a small capacitor across the inputs of the second stage (i.e. the bases of Q9 and Q10).
Excellent power supply rejection can be achieved by the use of a differential transimpedance stage as shown in figure 3. The second stage is formed by Q5–Q8, and its output is converted to single ended by the current mirror realised by Q9 and Q10; biasing is provided by I2.
Figure 3: Amplifier topology with differential transimpedance stage.
Besides the Miller compensation capacitor C2 there is now an additional capacitor (C1) which has an (although only second order) influence on compensation. It is required to make the drive from the input stage single-ended at high frequencies, as otherwise the output current of Q2 would bypass the Miller compensation loop at high frequencies.
The conversion of the differential output current of the input stage to a single- ended output voltage is, thanks to the ground connection of C1, carried out with respect to ground. Ripple of the negative power supply is present at the base of both Q5 and Q6; however this appears as a common-mode signal to the transimpedance stage and hence is rejected because of the differential nature of this stage. The rejection is mainly limited by mismatch of C1 and C2; for best results these should hence be 1% parts.
It cannot be stressed enough that C1 needs to be grounded for good power supply rejection. Most amplifiers that use a similar topology (and that I've evaluated), connect this capacitor to the collector of Q7; presumably in an attempt to make it a Miller compensation capacitor as well, but this cannot happen as there is no significant voltage swing at this node. However this arrangement will effectively connect C1 to the positive power supply rail through the current mirror input, putting power supply rejection back to the point of the simple two-stage amplifier of figure 1.
Also detrimental to the performance of this topology is the use of a standard current mirror instead of the active load formed by Q3 and Q4. The main disadvantage of this topology relates to the voltage headroom required by I2; it directly reduces available output voltage swing which is highly undesirable. Also both sourcing and sinking output current capability of the second stage is limited by I2; hence the support of very high slew rates will again be difficult at some point, particularly if the output stage demands substantial drive current.
As we have seen from this discussion of two-stage topologies there is no known architecture which simultaneously achieves inherently excellent power supply rejection and freedom from second-stage slew rate limits. In the following section I will present a novel amplifier topology which does just this.
3 The gain of one complementary half is defined as the transconductance of that differential pair times the corresponding Miller compensation capacitor. Gain mismatch can hence arise both from the input stage transconductances or the compensation capacitors.
3. New Push-Pull Transimpedance Stage
As shown above the main power supply rejection limitation in typical two-stage amplifier topologies arises from the reference of the input of the transimpedance stage to at least one supply rail. More specific, the emitter of the common-emitter transistor in the transimpedance stage is connected directly to the power supply, which then forwards power supply ripple to the input of the transimpedance stage.
From this node Miller compensation transfers the ripple to the second stage output. Can't we simply connect the emitter of the common-emitter transistor in the transimpedance stage to ground, in order to also reference the Miller compensation loop to ground? This is not straightforward, because the collector of this transistor needs to be able to swing nearly all the way from the negative to the positive power supply; furthermore, the input voltage of the second stage is then at a potential which is inconvenient to drive from the input stage without greatly limiting the common-mode input range of the differential pair.
Fortunately not straightforward does not mean impossible in this case. We can use folded cascodes both to level shift the output current of the first stage to the input of the transimpedance stage, and to free the collector of the common-emitter transistor from any significant voltage swing. Folded cascodes are non inverting stages and, being common-base transistor configurations, typically reduce stability margins of the global feedback loop by a small amount only. Hence there are only minor fundamental implementation problems to be expected.
Figure 4 depicts a first attempt to design such an amplifier. Q5 forms the folded cascode which acts as level shifter for the output current of the input stage, and Q8 provides the folded cascode for the output of the basic transimpedance stage realised by Q6 and Q7.
Figure 4: Amplifier with ground referenced second gain stage and folded cascodes for level shifting.
The input node of the transimpedance stage (the base of Q6) is now indeed, through the base-emitter junctions of Q6 and Q7, referenced to ground. It results that the basic power supply rejection will be high and independent of frequency.
At first it might look as if the collector current of Q7 were undefined; however, V2 forces a fixed voltage across, and hence a fixed current through, R5. Ignoring the base current loss of Q8, the difference between this current and that set by I3 is then, by the action of global feedback, enforced as collector current for Q7. Also noteworthy is the fact that there is just one compensation capacitor needed - there is no chance that capacitor mismatch can introduce distortion, instability or a power supply rejection limitation as observed for some prior art topologies.
While practical implementation of such a circuit is perfectly feasible, the output of the transimpedance stage is not yet a push-pull configuration and will have similar slew rate limits as the one from figure 1. The amplifier revealed by figure 5 fixes this.
Figure 5: Basic amplifier with novel push-pull transimpedance stage.
The transimpedance stage (Q7–Q12) is now arranged as complementary push-pull configuration. Unlike the amplifier from figure 2, there is no need for an explicit bias current control circuit; the voltage from Q7 emitter to Q8 emitter provides bias for Q9 and Q10. The input node of the transimpedance stage (the bases of Q7 and Q8) is still referenced to ground by the emitters of Q9 and Q10. Hence the basic power supply rejection is good.
As an additional change, both collectors of the input pair are now level shifted with folded cascodes (Q3 and Q4), and the current mirror (formed by Q5 and Q6) is placed after the cascodes. This minimises the impact of the folded cascode to collector current balance of the differential pair of the input stage, and with the dual folded cascode the differential pair is operated at very nearly equal collector voltage; this reduces secondary limitations to offset, drift, common-mode rejection and power supply rejection.
In the next sections we will look into the optimum practical realisation of amplifiers with this novel transimpedance stage, and explore several extensions and adaptations of it.
Coming up in Part 2: Biasing Considerations, stability and AC performance
 Douglas Self: Audio Power Amplifier Design Handbook, 5th edition, Focal Press, 2009
 Bob Cordell: Designing Audio Power Amplifiers, 1st edition, McGraw-Hill, 2010
 J. E. Solomon: TheMonolithicOp Amp: A Tutorial Study, IEEE J. Solid-State Circuits, vol. 9, no. 6, pp. 314–332, December 1974
 Bhupendra K. Ahuja: An Improved Frequency Compensation Technique for CMOS Operational Amplifiers, IEEE J. Solid-State Circuits, vol. SC-18, no. 6, pp. 629–633, December 1983
 Samuel Groner: Comments on Audio Power Amplifier Design Handbook by Douglas Self, February 2011, available for download from www.sg-acoustics.ch/analogue_audio/power_amplifiers/pdf/audio_power_amp_design_comments.pdf
 Bruno Putzeys: The F-word - or,why there is no such thing as too much feedback, Linear Audio, vol. 1, pp. 112–132, April 2011
 Royal A. Gosser, Jeffrey A. Townsend: Integrated-Circuit (IC) AmplifierWith Plural Complementary Stages, US Patent 5,537,079, filed December 1994, issued July 1996
 Giovanni Stochino: Ultra-fast amplifier, Electronics &WirelessWorld, pp. 835–841, October 1995
 Alberto Bilotti: Noise Characteristics of Current Mirror Sinks/Sources, IEEE J. Solid-State Circuits, vol. SC-10, no. 6, pp. 516–524, December 1975
 William H. Gross: New High Speed Amplifier Designs, Design Techniques and Layout Problems, Analog Circuit Design: Operational Amplifiers, Analog to Digital Convertors, Analog Computer Aided Design, Springer, 1993
 William F. Davis, Robert L. Vyne: Design Techniques for Improving the HF Response of a Monolithic JFET Operational Amplifier, IEEE J. Solid-State Circuits, vol. SC-19, no. 6, pp. 978–985, December 1984
 Graeme John Cohen: Double Balanced Microphone Amplifier, AES preprint, no. 2106, August 1984
 Bruno Putzeys: High-Performance Discrete Building Blocks for Balanced Audio Signal Processing, AES preprint, no. 6294, October 2004
About the author
Samuel Groner was born and currently lives in Zurich, Switzerland. He has been passionate about both art and science as long as he can remember. At present he works for Weiss Engineering Ltd. in the field of analogue hardware design and freelances as classical recording engineer/producer. Besides this, he teaches several courses at a local sound engineering school (ear training, classical music production and audio measurement) and enjoys a manifold activity as pianist, singer and choirmaster. If time permits, he is found on one of the numerous Swiss hiking trails, preferably in company with one of his cameras and a few sheets of black-and-white film. He holds a MSc degree in computer science and a MA degree as Tonmeister (recording engineer/producer).
This article originally appeared in Linear Audio Volume 2, September 2011. Linear Audio, a book-size printed tech audio resource, is published half-yearly by Jan Didden.
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