Editor's note: This excerpt from Embedded SOPC Design with Nios II Processor and Verilog Examples by Pong P. Chu appears courtesy of the editors at John Wiley & Sons Inc. In part 1, we reviewed SRAM, with a particular focus on timing and programming the control. In part 2, we did a similar review of SDRAM. Part 3 of this excerpt reviews methodology for testing memory. Please note, where appropriate, the examples use Alteraís SOPC Builder tool. Although SOPC Builder is in use by developers around the globe and supported by Altera, the company also has a newer tool called Qsys that does everything SOPC Builder does and more.
16.8 TESTING SYSTEM
We create a simple Nios II system to verify the operation of memory modules. The top-level diagram is shown in Figure 16.17. The system consists of a PLL core to generate the clock signal, a JTAG UART core to display messages on the console, and three memory cores, including an embedded on-chip memory, an SRAM controller, and an SDRAM controller. The testing program is stored in the on-chip memory. It first writes data to the SRAM and SDRAM modules and then reads it back to check errors.
Click image to enlarge.
Figure 16.17: Top-level diagram of memory testing system.16.8.1 Testing hardware configurationNios II system
We can create the testing Nios II system in SOPC Builder. The procedure is:
- Add and configure a Nios II/e processor and rename it cpu.
- Add an on-chip memory module of 16 KB and rename it onchip_mem.
- Add the SRAM controller module and rename it sram.
- Follow the procedure in Section 16.7 to add an SDRAM controller module and rename it sdram.
- Select the on-chip memory module for the reset and exception vectors.
- Add and configure a JTAG UART module and rename it jtag_uart.
- Add a system id module and rename it sysid.
- Follow the procedure in Section 16.7 to add an ALTPLL module and rename it pll. The Clock Setting panel of the SOPC Builder is updated to include two additional clocks, labeled pll_c0 and pll_c1, which are the two outputs of the pll module.
- Rename the external clock clk_50M and rename two PLL clocks clk_sys and clk_sdram, as shown in the top of Figure 16.18.
- In Clock column, verify that the external clk_50M clock is the clock source for the pll module and select clk_sys as the clock source for all other SOPC modules.
- Generate HDL and information files.
Although the basic steps are similar to those in Section 11.5.1, this procedure has several unique features. First, there are three memory modules in the system. Since we want to store a testing program in the on-chip memory module later, we must select it for the reset and exception vectors in step 5.
Second, because of the inclusion of a PLL module, the system contains three clock sources (one external clock and two PLL-generated clocks). If we click the Clock column of a module, a pull-down menu with three clock sources appears. Because we want to use the PLL-generated clk_sys to drive the Nios II system, we must change the clock source for all modules, as in step 10. The screen capture of the completed system is shown in Figure 16.18.
Finally, the economy core (i.e., Nios life) must be selected for the testing system because the data cache of fast core may interfere with the memory testing operation.
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Figure 16.18: Screen capture of SOPC Builder.Top-level HDL file
After the HDL files are generated by SOPC Builder, we can create a top-level module that incorporates the Nios II system. The HDL code is shown in Listing 16.2.
Listing 16.2: Top-level memory testing circuit
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The code performs mapping between the ports of the instantiated Nios II system and the 1/0 signals on the DEl board. Note that one input clock and two out≠ put clocks of the PLL module are also shown as explicit ports in the instantiated Nios II system. The PLL's clk_50M
clock is mapped to the clk
port of the entity, which is connected to DEl board's 50-MHz oscillator, and the PLL's clk_sdram
clock is mapped to the dram_clk
port of the entity, which is connected to the external SDRAM device's clock input. The PLL's clk_sys
clock is not used and thus mapped to open. If the system inside the FPGA device contains other synchronous subsystems, their clock signals should be connected to clk_sys