The basic RTL of this implementation is as follows
reg postcale_count, next_count
assign postscale_count <= next_count
always (@ posedge clock_in)
postscale_count <= postscale_count + next_count
Figure 3. Div decode divider implementation
value of postscale_count register is updated on every rising edge of
the input clock that is to be divided. The divided clock can be tapped
from the MSB of the postscale_count register. The value of the next
count register depends upon the division factor.
- These dividers are the simplest in terms of RTL complexity.
generate 50% duty cycle output clocks and do not result in an inherent
skew like ripple dividers because the divided clock is always generated
at one point.
- These dividers are restricted to 2N division only.