Structural test is the foundation of the majority of IC production testing. The idea of structural test is that the entire chip operation doesn’t need to be known. Instead, the structural pieces and their connections are individually verified. This is a very effective approach and enables both high levels of defect detection and automation since the complex IC behavior is broken down into simple pieces. Scan testing verifies the combinational logic and state elements like flip-flops and latches, whereas, memory built-in self test (BIST) is used to test RAM and other memory devices. The problem is that timing defects between the RAM and surrounding logic, often referred to as “shadow logic,” could be missed. ??It is easy to miss testing for timing defects between memories and logic. >>Continue reading this article on Test&Measurement World for tips to avoid this.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.