Breaking News
Design How-To

A new audio amplifier topology with push-pull transimpedance stage - Part 2: Biasing, stability and AC performance

5. Stability and AC Performance
9/26/2012 03:05 PM EDT
2 comments
NO RATINGS
1 saves
< Previous Page 2 / 4 Next >
More Related Links
View Comments: Newest First | Oldest First | Threaded View
WKetel
User Rank
Author
re: A new audio amplifier topology with push-pull transimpedance stage - Part 2: Biasing, stability and AC performance
WKetel   10/4/2012 12:48:59 AM
NO RATINGS
1 saves
I have always worked to get rid of all the power supply noise so that the high level of power supply noise rejection that was required was not so great. In addition, the tolerance of components needed to filter out power supply noise are far less critical than those needed for good amplifier PSRR design. Probably a combination of the two methods would be the best choice. Of course, optimizing for the minimum cost was never the highest priority for our group, nor for our customers. Somebody else can always make something cheaper and not quite as good.

Raul_77
User Rank
Author
re: A new audio amplifier topology with push-pull transimpedance stage - Part 2: Biasing, stability and AC performance
Raul_77   9/29/2012 1:21:12 PM
NO RATINGS
1 saves
Hi, sorry for my english. About the power supply rejection, in this old Luxman: http://www.eserviceinfo.com/download.php?fileid=48149 can be see the use of differents supplies for each stage of the power amp in a cheap and good way, the effect in the sound quality are very good.

Most Recent Comments
michigan0
 
SteveHarris0
 
realjjj
 
SteveHarris0
 
SteveHarris0
 
VicVat
 
Les_Slater
 
SSDWEM
 
witeken
Most Recent Messages
9/25/2016
4:48:30 PM
michigan0 Sang Kim First, 28nm bulk is in volume manufacturing for several years by the major semiconductor companies but not 28nm FDSOI today yet. Why not? Simply because unlike 28nm bulk the LDD(Lightly Doped Drain) to minimize hot carrier generation can't be implemented in 28nm FDSOI. Furthermore, hot carrier reliability becomes worse with scaling, That is the major reason why 28nm FDSOI is not manufacturable today and will not be. Second, how can you suppress the leakage currents from such ultra short 7nm due to the short channel effects? How thin SOI thickness is required to prevent punch-through of un-dopped 7nm FDSOI? Possibly less than 4nm. Depositing such an ultra thin film less then 4nm filum uniformly and reliably over 12" wafers at the manufacturing line is extremely difficult or not even manufacturable. If not manufacturable, the 7nm FDSOI debate is over!Third, what happens when hot carriers are generated near the drain at normal operation of 7nm FDSOI? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can't go to the substrate because of the thin BOX layer. Some holes may become trapped at the BOX layer causing Vt shift. However, the vast majority of holes drift through the the un-dopped SOI channel toward the N+Source,...

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed