This article originally appeared in Linear Audio Volume 2, September 2011. Linear Audio, a book-size printed tech audio resource, is published half-yearly by Jan Didden.
[Part 1 introduces an audio amplifier topology which uses a novel push-pull transimpedance stage that offers a substantial improvement in power supply rejection over standard amplifier configurations.]
4. Biasing Considerations
The first thing to get right in a circuit design is the biasing conditions. So I will, first of all, discuss the necessary considerations in this respect. Please consider figure 6 for this, which shows several additional circuit elements that are essential, or at least very helpful, for a practical realisation.
There are three fundamental bias currents to be chosen for this novel transimpedance stage: the collector current of the emitter followers Q8 and Q9, that of the common-emitter transistors Q10 and Q11, and finally the current in the folded cascodes formed by Q14 and Q15. Needless to say, the collector current of complementary pairs (e.g., Q8 and Q9) should be set to approximately equal values. There are various trade-offs associated with the selection of these bias conditions. Detailed discussion of these is beyond the scope of this article, so I'm just quoting suggested values which will be found to work well in most typical power amplifier designs:
- 0.5–1 mA for Q8 and Q9
- 5–2 mA for Q10 and Q11
- Use the same, or a slightly higher, collector current for Q14 and Q15 as for Q10 and Q11.
The collector current for Q8 and Q9 is easily set by selecting appropriate values for R7 and R8. Biasing Q10 and Q11 requires a bit more thought, however. As mentioned in the previous section, an explicit bias current control circuit will not be required for the new push-pull transimpedance stage. However, to mitigate the sensitivity to transistor tolerances and thermal effects, the addition of emitter resistors is necessary. In figure 6, R11 and R12 realise this. In most cases choosing their values such that they each carry about a 100 mV voltage drop at the nominal collector current of Q1 and Q11 will be sufficient for good bias current stability.
Figure 6: More detailed amplifier schematic using the new second stage topology.
Minimising the value of the emitter resistors is advantageous as this lowers the sensitivity to loading of the second stage output node (details on this can be found in ), so going above the suggested 100 mV voltage drop is not advised. Once the emitter resistor value is determined, an appropriate bias voltage is set up by selecting R9 and R10. Simulation can be helpful to derive an initial estimate for the value of these parts, however experimental verification will usually be needed.
The collector current of the folded cascodes (Q14 and Q15) is set both by the emitter resistors (R13 and R14) and the base reference voltage sources V2 and V3. To maximise available output voltage swing the DC voltage drop across the emitter resistors should be minimised; a lower limit of about 200 mV is set by the need that the emitter impedance of the folded cascode transistor (given by the reciprocal of its transconductance) is small compared to the emitter resistor, such that most of the AC collector current of Q10 and Q11 actually flows into the emitter of the corresponding folded cascode (and thus to the output node), rather than into the emitter resistor (and thereafter into the power supply, where it does not produce any usable output).
After discussion of the biasing considerations of the transimpedance stage, we will turn our attention to the folded cascodes of the input stage (Q3 and Q4 in figure 6). As these folded cascodes are part of the input stage, they must be carefully designed to not impair the voltage noise of the amplifier (such considerations are essentially negligible in the second stage, where there is a substantial amount of loop gain available to reduce the impact of the corresponding folded cascodes).
That's particularly important if, as routinely done in audio power amplifiers, the input stage transconductance is reduced by the addition of emitter resistors in the differential pair (note R1 and R2). While the emitter degeneration is very useful for improving input stage distortion and slew rate [1, 2], it also pronounces noise contributions from following stages.
As detailed in the appendix, there are several design strategies available to minimise the impact of the folded cascodes:
- Maximise the value of the emitter resistors by minimising the quiescent current of the folded cascode transistor and the use of a voltage reference with large DC voltage.
- Use a voltage reference with low noise and low impedance.
- Choose transistors with high hFE and low excess noise.
If these strategies are combined they will ensure that amplifier performance is not significantly degraded by the presence of the folded cascodes. There's one caveat regarding the quiescent current of the folded cascode transistors: if it is chosen lower than the collector current of the input differential pair, additional distortion at high frequencies might result (because at peak output currents of the differential pair one or the other folded cascode transistor will switch fully off ). Usually the most suitable bias condition for the folded cascode transistors is hence a collector current equivalent to, or slightly above, that of the transistors of the input differential pair.
The current mirror (Q6 and Q7 in figure 6) has a very similar impact on the voltage noise of the amplifier as the folded cascodes Q3 and Q4. As indicated in the appendix, the procedures to minimise its contribution are very similar to those of the folded cascode.Most important, the emitter resistors R5 and R6 should have a large value [5, 9]. Unlike the prior art topologies from figure 1–3, there is plenty of voltage headroom at the current mirror output available, which allows the use of rather large emitter resistors without pushing the current mirror close to saturation.
Figure 6 reveals a last enhancement for the input stage. The common-base transistor Q5 is introduced to keep the folded cascode transistors Q3 and Q4 at approximately the same collector-emitter voltage. This minimises offset due to Early effect and different thermal operating points. Moreover, the base current of this additional transistor partially cancels the base current errors of the current mirror. This further reduces amplifier offset voltage.