We’re settling down to autumn in the northern hemisphere after the hustle and bustle of summer. In some ways, it's a relief—between holidays, vacations, company picnics, and the inevitable visiting guests and family, it seems like there's never enough time to get all of the work done. Doubtlessly, somewhere along the line you simply couldn't get to one of the newsletters. Want to catch up on what you missed? We've gathered together a selection of summer's top design features, just for you. Book excerpt: SRAM and SDRAM controllers for FPGAs, part 3 Learn about testing hardware and software for SRAM and SDRAM. Book excerpt: SRAM and SDRAM controllers for FPGAs, part 2 Learn what you need to know about DRAM and programming memory controllers for FPGAs. Book excerpt: SRAM and SDRAM controllers for FPGAs, part 1 Learn what you need to know about memory and programming memory controllers for FPGAs. Breaking through the embedded memory bottleneck, part 2 Algorithmic memory leverages erasure encoding to allow simultaneous access of data in the same location without memory bank conflicts or stalls. Breaking through the embedded memory bottleneck, part 1 Memory operations per second (MOPS) provides a better metric for assessing new techniques like algorithmic memory. Diagnostic and repair tools for embedded memory boost SoC yields Memory test, repair, and diagnostic solutions can improve both the manufacturing process and device performance. SLC vs MLC: Which works best for high-reliability applications? Although multi-level cell NAND flash offers a cost advantage, single-level cell NAND flash delivers longer lifetime, lower error rates, and better performance for mission-critical applications. Anti-fuse memory provides robust, secure NVM option Non-volatile memory technology addresses demands of SoCs controlling 24/7 connected devices. Technology Roundup: phase-change memory How it works, the latest advances, and progress toward commercial viability. Technology Roundup: NAND flash A look at the basics, the evolution of the technology, and design tips. Understanding DDR SDRAM timing parameters Learn about various timing parameters and their impact on the performance of the DRAM. Improved memory throughput using serial NOR flash - part 2 Discover protocol-level upgrades and hardware changes that can speed serial NOR flash memory. Improved memory throughput using serial NOR flash - part 1 Discover system-level and memory-device strategies that allow higher read throughput for economical NOR flash memory. Multi-die DRAM packaging technology drives down Ultrabook platform cost – part 2 Quad face down (QFD) technology delivers the memory functionality of a 1-GB SODIMM in a compact, 243-ball package. Multi-die DRAM packaging technology drives down Ultrabook platform cost – part 1 By leveraging face-down architecture, design provides the memory functionality of an SODIMM in a single package.
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January 2016 Cartoon Caption Contest
Bob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.