Timing defines the performance of a chip. If timing constraints are not met, the chip is as good as dead. Any extra pessimism in timing analysis not only requires more time to fix the critical paths but could negatively impact other important parameters such as power and area. In the worst case, it might leave no option but to reduce the functional frequency of the design. On the other hand, optimism in timing analysis might result in silicon failure. Finding a bug in silicon can be a ponderous task, not to mention the monetary and goodwill loss for design companies. It is therefore prudent to remove undue pessimism and optimism from timing analysis.
Clock architectures have become fairly complex for modern SoCs. In synchronous design, clock controls the switching of sequential elements of the design and functionality of logic is ensured through meeting the required setup and hold checks. Timing engineers must remove any undue pessimism/optimism in the calculation of clock path delay because it can be detrimental for the design.
On-chip variation is one of the most important factors that necessitate pessimism introduction in timing analysis. It refers to the intra-die variations that may exist between different cells in different parts of the chip under the same operating condition. These variations may be:
- Variation in the manufacturing process
- Variation in the voltage: Due to different IR drops for different cells
- Variation in the temperature: Due to formation of localized hot-spots on the chip.
Timing engineers model these variation in the form of derates. Applying derates on clock paths is the most popular and acceptable way to model these variations. Assuming 10% derates, for both early and late paths, delay X for a cell under an operating point can be modeled as 0.9X as capture clock path delay and 1.1X as the launch clock path delay for setup analysis.
Common clock path pessimism is one of the most common sources of pessimism in the design.Common path pessimism
Common path pessimism arises when the launching and capturing clocks share a common path. The difference between the max delay and min delay of this common clock path segment is called the common path pessimism. EDA tools take care of this using Common Path Pessimism Removal (CPPR).
Figure 1: Common Clock Path Pessimism
There are two ways of calculating common path pessimism:
- Critical-path based approach (CPPR):
a) Timing analysis tools finds the top critical paths with CPPR off.
b) Only these critical paths are re-evaluated considering CPPR for the common clock path.
While this method offers the advantage of being relatively fast compared to the Exhaustive Approach, it can miss critical paths. Hence for some corner cases, it might lead to an optimistic timing analysis.
- Exhaustive approach: This method does an exhaustive CPPR analysis and therefore does not miss any critical path. However, analysis requires more memory and CPU resources compared to those required for the critical-path based method.
Assuming two reg-2-reg timing paths with the same data path delay, the path with the lesser common clock path might get missed using critical-path based approach. Consider the following example:
Figure 2: Case study showing how path-based approach can be optimistic
As evident from Figure 2, path 2 was critical with CPPR off, but with CPPR on, path 1 became more critical.
Timing engineers therefore tend to analyze their design using the exhaustive approach once the design has achieved logic freeze.