Whether your application is focused on wireless communications or instrumentation, the performance bottleneck is often the dynamic range of the analog-to-digital converter (ADC).Dynamic range is often a key parameter within signal processing systems and a shortfall can limit the quality and range of signals that can be received. The technical progress made on improving this gateway between the analog and digital world has not kept pace with Moore’s law because the challenges are more fundamental than simply reducing transistor sizes.Methods to increase ADC dynamic range are always of interest although each solution often suits particular applications.
As an example of pushing ADC dynamic range beyond what is currently available, the engineers at RFEL were confronted with an application where a customer required an analog-to-digital conversion with a 74dB dynamic range at 800MSPS.Most available ADCs at this rate were typically 52dB, i.e. 8.3 effective number of bits (ENOB).This represented a significant 22dB shortfall, which had to be resolved for the project to be feasible.
Various techniques for extending dynamic range were considered taking into account their advantages and disadvantages:
Increase the sample rate. Sampling at a higher rate and subsequently band limiting and decimating the output can reduce the quantisation noise floor of an ADC.This has the effect of filtering out of band noise sources and, in theory (assuming all noise is incoherent in nature); the dynamic range can be increased by 3dB for each doubling of sample rate.However, at higher sample frequencies the gains are modest because the ENOB performance of high rate ADCs also degrades. The ADC cost should also be considered as this usually increases with sample rate.
Interleaved ADCs. A more common solution is to use multiple lower rate ADCs, which inherently have a better ENOB, to consecutively sample the input signal in an interleaved manner.The dynamic range gains are very much dependent upon the ENOB improvement of the lower rate converters which tends to be more significant when targeting high sample rates.To retain any performance gains, careful consideration must be given to amplitude and phase matching between ADCs.This can involve gain matching, PLL selection and attention to PCB layout.The input bandwidth of the lower rate ADCs must of course be sufficient for the bandwidth of the signal of interest.
Non-linear gain stage. If the input signal is passed through a device with a non-linear gain, then the target dynamic range of the input signal can be mapped onto the available input range of the ADC.This effectively produces an ADC quantisation step size, which increases with the amplitude of the input signal.A disadvantage of this technique is that the signal must be restored by subsequent signal processing, which often requires signal training to guarantee accuracy.Also quantisation noise is dominated by the largest part of the signal.
Stacked ADCs. To make a significant improvement in dynamic range, a stacked ADC architecture can be used. In this approach, the signal is split into multiple paths, each with a different gain before input to the ADC.If for example three ADCs are used, they would capture large, medium and small signals respectively and the final output would be selected from the most appropriate ADC.This principle has an obvious problem because although one signal can be tracked over a large dynamic range, the instantaneous dynamic range (i.e. the capability to receive large and small signals at the same time) is actually degraded.Another potential issue is that each path must be carefully matched to align phase, amplitude and frequency responses.
For the project, the large 22dB increase in dynamic range could not be realistically achieved using methods (1) or (2).Technique (3) was feasible; however it was rejected due to the large quantisation steps for large input signals and the overhead of signal training.Further analysis of the system requirements revealed that the customer’s monitoring application did not require a high instantaneous dynamic range; therefore the feasibility of solution (4) was investigated further.
This technique is not suitable for applications which have signal components at very different input levels. As your mention, when one of the gain paths saturates, the signal will be sourced from a lower gain non-saturated path. It is important to note that the saturated ADC must still recover quickly when the signal is back within its range.
I wonder how the system avoids over-drive/saturation of the mid-range and low-end ADCs when a very strong signal (within the high-end range) is present at the very input before the split, for example in a broadband multi-carrier scenario where multiple different narrowband signals may get into the system each with very different input levels.
Or probably the application as discuss by Mr. Fifield is for a single wideband signal therefore saturation of the lower-end ADCs can be discarded.
Anyway, very interesting setup.
More than two decades ago I got into a similar problem for current measurement in an energy meter requiring high dynamic range. I easily solved the problem by using a programmable gain amplifier using analog switches and an op-amp. It worked like a charm for such a slow speed application using a home grown double sided board.
Quick question on footnote :
"The calculation for ENOB is: (dynamic range – 1.76)/6.02"
I've never seen this equation before: Is it specific to the system, or does this apply to any number of ADC's?
The design and test of this stacked ADC is quite interesting. To perfect this the analog gain amplifiers need to have very good matching in phase and amplitude. Probably i feel that if there is a control with feed back between these gain stages in the stacked system the performance may be further improved.
A few years ago I had a problem digitizing heading rate for a robot. Then I realized I needed heading data in two distinct modes. When traveling in a straight line I needed high resolution heading rate data near zero. When the robot was turning I needed low resolution data over the full voltage range.
I easily solved the problem by using two 8 bit A/D channels on the same input, one through a clamped x32 amplifier. When turning I used the non-amplified signal. When traveling straight I used the amplified signal.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.