To achieve 74dB of dynamic range requires roughly 12 (74/6) bits, however it was necessary to add on the minimum signal to noise ratio (SNR) that the system required which, in this case, is approximated at an additional 4bits. The total signal range is therefore roughly 16 (12+4) bits. We previously mentioned that phase and amplitude matching was important, therefore we would like to have identical ADCs in a dual, triple or quad packaged IC. The best option considering device cost and performance was an e2v EV8AQ160 - 8bit quad packaged device. To meet the dynamic range and SNR requirements, three of the four packaged ADCs were used to cover the full 16-bit range. The ADCs were allocated such that the most sensitive ‘ADC_Low’ detects bits 1:8, ‘ADC_Mid’ detects bits 4:12 and ‘ADC_High’ detect bits 8:16 (see Figure 1). This covers the full 16bit range fulfilling the dynamic range requirement and provides a four-bit overlap to satisfy the SNR requirement.
The design and layout of the analogue input network is another potential minefield especially because the input signal is split into three different gain paths. To maintain a consistent amplitude, phase and frequency response each path contains an identical active gain stage which is preceded by a passive attenuator of 0dB, 24dB and 48dB for the high (bits 1:8), medium (bits 4:12) and low (bits 8:16) gain paths respectively.
To reduce noise, linear power regulators were used and the high gain signal path was positioned away from other potential sources of noise.
The analog and digital components were designed, simulated and then fabricated onto a 14-layer PCB.
The high layer count was required to enable multiple BGA devices to be routed within a small area.
The performance of the design was tested over the complete signal range under various environmental and EMC conditions to ensure robust operation. Figure 2 below shows the combined 16-bit output for an input signal at full scale (low gain path active) and then again after it has been attenuated by 76dB (high gain path active).
The pulse shape can clearly be observed in both figures. The second figure shows that our efforts to mitigate noise have paid off as we are successfully operating close to the quantization noise floor of the device.
This article focused upon extending the dynamic range of the analogue-to-digital conversion process.
In the final product this was the first enabling step before useful information within the input signals could be extracted through digital signal processing. The processing was carried out within multiple high-speed FPGAs before results are sent out over a network connection – which is fodder for a separate article.
About the Author
, MSc CEng MIET, Senior Digital Systems Design Engineer at RFEL studied at the University of Manchester Institute of Science and Technology (UMIST), where he received a BSc in Electrical and Electronic engineering and an MSc in Instrumentation and Analytical science. He has worked in wireless communications as a Senior Research Scientist at Philips Research Labs (1995-2005), and as a Senior Scientist at NXP Semiconductors UK (2006-2008), before joining RF Engines. An active member of ETSI RES10 and BRAN standardisation bodies, he worked on prototype OFDM demonstration systems, and has filed 15 wireless system related patents. As digital processing speeds increased, he was involved with the development of early Software Defined Radio (SDR) architectures, using digital techniques to remove analogue functionality from systems such as GSM, CDMA2000, UMTS, 802.11a/g/n-20/n-40, GPS and Bluetooth.
 Moore’s law is infamous for its prediction of the rate at which silicon technology will evolve
 The calculation for ENOB is: (dynamic range – 1.76)/6.02