LONDON – Want to know how to get an applications processor for a smartphone working right the first time? Or how to cut the leakage power in a leading-edge chip or how to bring-up and debug an Android platform?
Help is on the way..
Speakers from EDA software vendors Cadence Design Systems Inc. and Synopsys Inc. – and also from their chip- and system-designing users – will be presenting on EDA topics as part of the sponsored sessions at ARM TechCon, which is set for Oct. 30 to Nov. 1 at the Santa Clara Convention Center. There are more than 40 sponsored sessions covering a breadth of topics listed at the ARM TechCon website and because they are sponsored attendance is available for free.
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ARM TechCon is annual three-day conference for the design community gathered around intellectual property licensor ARM Holdings (Cambridge, England). The event is organized by UBM Electronics, the publisher of EE Times.
On the EDA front, Cadence will be contributing to the discussion of pairing "big-little" processors for power efficiency at the conference with a presentation (SS-105) on Tuesday (Oct. 30) at 10:30 a.m.followed an hour letter by a joint presentation with an ARM speaker (SS-106) entitled "Lessons learned from a 28-nm multicore Cortex-A7 low power implementation."
The second paper will discuss how to use a Cadence RTL-to-GDSII design flow to understand and tune a big-little design. This includes power intent capture using Common Power Format specifications and how to use Encounter software for such things as clock optimization. Also on the agenda are low-power verification and equivalence checking.
At 3:10 p.m. on Tuesday (Oct. 30), Luke Lang, Cadence director of engineering, will also be providing guidance (SS-108) on how to design low-power interfaces around a Cortex-M0 microcontroller core, using customer examples. Typical applications for such M0-based microcontroller would be the so-called Internet-of-things.
EDA tools from Synopsys are set to be discussed at 2:10 p.m. on Tuesday (Oct. 30) (SS-104) by Brian Miller, a physical implementation engineer at Samsung (Austin, Texas). Miller is set to describe how the Synopsys' Galaxy tools were used to design a Cortex-A15 processor for mobile applications. The Q&A at the end should also a chance for the audience to ask the questions that they might not ask of Synopsys.
Another Oct. 30 session (SS-101) will discuss how to achieve gigahertz-plus performance for a Cortex-A15 IC using Design Compiler and IC Compiler. Topics up for discussion include clock-tree synthesis, top-level timing closure and leakage power optimization. Finally, the presenters will share customer results on a production tapeout of an ARM Cortex-A15 processor to illustrate the successful application of these performance/power enabling techniques.
Oct. 30, the opening day of ARM TechCon is designated chip design day. But EDA is also represented on Oct. 31 and Nov. 1, the software and systems days.
Sessions on Wednesday (Oct. 31) include prototyping and early software development for ARM-based embedded systems (SS-235), Android platform debug (SS-207) and on Thursday a presentation from a couple of Synopsys authors (SS-301) will explain how to optimize the performance of the AMBA on-chip interconnect.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.