The first article in this series on memory test explained the nature of the memory test challenge in the industry today. The second article described several non-intrusive debug and test technologies, including functional test, processor-controlled test,boundary-scan test, FPGA-controlled test and others. Beginning with functional test, this, the final article in the series, takes a closer look at the tradeoffs among the non-intrusive methods and discusses how they have been implemented in the industry.
Functional test has also been applied to memories for years, but it can only be brought to bear late in the development cycle when the board is fully functional or close to fully functional. As a result, functional tests are very difficult to apply to boards with a problem, bug, defect or error. Functional tests typically are applied with the board in a test jig or when the board is in a fully configured system. In addition, their diagnostic granularity may be very limited.
More recently, third-party pseudo-functional test tools have been able to overcome many of the difficulties of classic functional test and reduce the risks that a test development process late in the design cycle typically poses. For example, processor-controlled test (PCT) tools for embedded instruments apply pseudo-functional test routines independently of the board’s functional firmware or operating software. PCT test routines can be applied by a processor without requiring a functional firmware environment. PCT tools appropriate the processor’s capabilities by way of its debug port. If the processor is connected directly to on-board memory, a PCT tool can apply its pseudo-functional test routines originating from the processor to test memory. As a result, test teams can apply pseudo-functional memory tests during the early stages of board bring-up without having to wait for the design’s operating firmware. In addition, the validity and comprehensive nature of PCT’s test routines have been verified over many different designs from many board manufacturers. The comprehensiveness of PCT’s memory test routines have themselves been fully field tested.
Memory has been tested with standalone boundary-scan (IEEE 1149.1/ JTAG) testers for more than a decade. Currently though, certain new memories may be outpacing the ability of board-level boundary scan since the minimum clock and data rates of the memory devices may exceed the maximum board test clock frequency (TCK) of boundary scan. So, for modern high-speed designs, the application of boundary-scan test (BST) as a tool for memory test may be limited, but only time will tell.
FPGA-controlled test (FCT) tools are emerging as an attractive alternative for debugging and testing memory. Borrowing a functional FPGA on a board as the basis for testing memory during prototype board bring-up and manufacturing has been implemented for years, but each such implementation has been developed by the board test provider and each test suite typically involves custom or functional development of test instruments and custom access protocols. The difficulty here is that the instruments embedded in the FPGAs are custom crafted for each board design with no, or limited, intended re-use. To access the full article, click here.