The ARM Cortex-A family of processor cores is gaining traction and success in many applications such as set-top box, smart phones, mobile computing, gaming, DTV and many different ‘internet connected’ devices. In a number of applications, it is not only important to drive multi-processor capability, but to improve single-threaded performance.
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The Cortex-A9 Processor Optimization Pack (POP) is a product that allows partners to quickly implement a Cortex-A family processor to achieve high performance while maintaining the advantages of the ARM low-power processor architecture. The ARM POP gives a partner implementation team a time-to-market advantage, lower risk, design flexibility and headroom for further customization. POPs also allow customers to address fast-changing consumer products.
ARM has developed a family of POP solutions that provide ARM partners with a solution to achieve power, performance and area (PPA) leadership with ARM Cortex-A implementations. A POP is composed of three elements necessary to achieve an optimized ARM core implementation. First, it contains ARM Artisan Physical IP logic libraries and memory instances that are specifically tuned for a given ARM core and process technology. This Physical IP is developed through a tightly coupled collaboration with ARM Processor Division engineers in an iterative process to identify the optimal results.
Second, it includes a comprehensive benchmarking report to document the exact conditions and results ARM achieved for the core implementation. Finally, it includes a POP Implementation Guide and knowledge transfer that details the methodology used to achieve the result, to enable the end customer to achieve the same implementation quickly and at low risk.
ARM has developed POPs to drive partner opportunities on leading foundry nodes such as TSMC 40nm and 28nm, Samsung 32nm, and GLOBALFOUNDRIES 28nm process nodes.
Physical IP Components
The Physical IP developed for the POP includes fast cache instances specific to the Cortex-A9 MP processor, high-performance standard cell libraries, optimized standard cells (High Performance Kit - HPK) and a power management kit (PMK). This IP enables multiple voltage domains and voltage isolation for leakage mitigation and further power reduction.
The multi-channel (MC) multi-Vt standard cell architectures are a collection of standard cells implemented with different threshold transistors and channel lengths which are foot-print compatible. The MC libraries provide the implementation engineer further opportunity for leakage optimization; tradeoffs can be easily made on performance and power by swapping the shorter channel length cells with the longer channel length cells to reduce leakage. The library variants can provide opportunity for significant power reduction within the processor implementation.
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