XMOS has now labeled its silicon as the xCore multicore microcontrollers and claims they have the low latency, fast I/O response and
deterministic performance required for real-time applications in consumer, audio, industrial, and automotive markets.
XMOS silicon continues to be the XS1-L1, XS1-L2 and XS1-G4. These have 1, 2 and 4 physical processor cores, respectively. However, XMOS is stressing the ability to host 8, 16 and 32 logical cores on these chips respectively.
This is enabled through the eight-fold time-slicing of processing that is done to better match memory access to the ALU pipeline performance. The availability of these "virtual" processors cores is a key part of the performance and responsiveness of the chips and is reflected upwards through the software development stack.
"The embedded market represents a $76 billion opportunity overall, and our xCore multicore microcontrollers offer significant advantages over traditional MCUs. xTIMEcomposer and xSOFTip allow developers familiar with C to access deterministic multicore performance more easily than ever before," said Nigel Toon, President and CEO of XMOS.
"System designers understand the limitations of traditional 8-, 16- and 32-bit MCUs in embedded applications, but they like their ease of use and simple development environments," Nigel continued. "They are now looking to multicore alternatives that can meet critical I/O response times, perform multiple tasks concurrently and support new interface standards: but they want the same easy-to-use development environment. As embedded systems continue to become more complex, xCore, supported by xTIMEcomposer and xSOFTip, meets this rapidly growing need."
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Software downloads from unique individuals and companies has exceeded 3,000. XMOS claims more than 1,000 active users of its software tools.
Well, I know they have been active in bringing out new devices - the most recent ones having a USB 2.0 PHY integrated in the chip.
However, there are least some architectural and software issues involved in using more than 64KB memory, so it is not quite as simple as putting a bigger SRAM macro in the design. So I'm not going to put money on bigger ram blocks in the next versions - but I would definitely like to see it in the future.
The other big problems I see with the XMOS lie with their development tools and the limitations of the "XC" language. But it is quite possible that this has changed now with the new tools they have released - I haven't tried them, and it would be unfair to complain about old problems before checking if they are now fixed.
You make a good point about lack of memory.
CEO Nigel Toon indicated that more components are in the pipeline, but did not wish to tip his hand about what is coming in the next three to six months.
So maybe XMOS is addressing that with a respin of silicon - or perhaps not. We wait to find out.
The XMOS chips are a nice architecture, but they suffer greatly from a lack of memory. There is just 64K per core for both program and data, and no sensible way to connect external memories (you can make a memory interface in software, but that uses up most of the pins and resources on the device!).
With at least 512 KB ram per core, and preferably with flash for bootloading on chip, these would be far more useful devices.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.