In SFR radar, clutter interferes with target detection, making it difficult to find the actual number of targets or even causing it to fail in detecting small targets. Finding a closed-form analytical solution that enables target detection to be analyzed in the presence of this clutter is also difficult. Because of the significance in analyzing these types of scenarios, simulation becomes critically important, as does the use of a platform solution for simulation of SFR systems under real-world environments. The platform can also be used for verification and testing of SFR systems. The simulation platform with test environment must include return signal radar cross section (RCS) and background clutter.
To better understand how such a platform might be used to design, verify and test a SFR system, a template SFR design is provided below. By customizing the template SFR design for their own systems, engineers can run simulations in the platform to evaluate the design’s performance. When design simulation is combined with test equipment, the simulation platform can also be used as a test platform for SFR component hardware testing. As an example, an SFR system with two target returns and ground clutter is presented in which the platform is used for both simulation and hardware test.
Simulating an SFR system
Consider the basic SFR design shown in Figure 2. In the signal generator, a SFR source is followed by an RF modulator, then two target models and a clutter model are used. At the SFR receiver input, received signals include target return and clutter.
Figure 2: This example of an SFR simulation is performed using Agilent Technologies’ SystemVue electronic system level design platform.
The received signal is measured at the input of the SFR and displayed in Figure 3. Note that the plot of frequency versus time in Figure 3C, is in keeping with what one would expect for the SFR signals based on the carrier frequency calculation previously described. The unwrapped phase is also expected. Additionally, the SFR receiver works fine in simulation.
Figure 3. Shown here is the spectrum (A), magnitude of the waveform that reflects the random characters of the target return as well as the clutter property (B), frequency hopping in the received signal (C), and the unwrapped phase (D) of a received SF radar signal measured at the receiver input.
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Figure 4 shows that using this high-resolution SFR design, two targets close to one another can be easily detected. To detect the same two targets using a pulse radar, the pulse width would have to be increased at least 8 times, significantly increasing system cost.
Figure 4. A high-resolution SFR design was used to detect these two targets near one another.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.