Breaking News
Design How-To

MEMS device downsizes clock generator

10/23/2012 12:05 PM EDT
6 comments
NO RATINGS
More Related Links
View Comments: Newest First | Oldest First | Threaded View
docdivakar
User Rank
Author
re: MEMS device downsizes clock generator
docdivakar   11/13/2012 5:52:25 PM
NO RATINGS
The opinions of commentators above seem to indicate MEMS timing devices are currently not a replacements for OCXO' or TCXO's and/or other non-MEMS timing devices that appear to have cost & performance advantages. It would be nice to see poster's like @psevalia contribute a comparative study of this... MP Divakar

wishboneash
User Rank
Author
re: MEMS device downsizes clock generator
wishboneash   10/24/2012 9:37:01 PM
NO RATINGS
Have to agree. MEMS timing devices are a solution looking for a problem. MEMS technology is better served for accelerometers, sensors and other miniaturized devices where the competing solutions converting mechanical to electrical signals are not viable or too expensive (in smartphones, tablets, automobiles etc).

gsdg90
User Rank
Author
re: MEMS device downsizes clock generator
gsdg90   10/24/2012 5:33:45 PM
NO RATINGS
Agreed that the frac-n approach is very problematic. Integer-N approaches rely upon a tunable reference oscillator which is stabilized across temperature and process. That works in the lab at low volume for short periods of time, but it is a million miles from capitalizing upon mature and well understood semiconductor processes. Quartz has nothing to fear, as these integer-n approaches are just science projects.

wishboneash
User Rank
Author
re: MEMS device downsizes clock generator
wishboneash   10/24/2012 3:38:00 PM
NO RATINGS
There is the problem of a fractional-N PLL to bring the frequency within tolerance. This adds jitter and power. Quartz still reigns when it comes to high-performance frequency generation. Solutions getting rid of the frac-N PLL will eventually beat out companies like Discera and SiTime. And there are a few companies already out there using CMOS based or other forms of tuned resonators. The quartz solution gets rid of the need for two cascaded PLLs needed when the output frequency is the GHz range. A single PLL coupled to an external quartz xtal or VCXO will have much better performance with less power.

gsdg90
User Rank
Author
re: MEMS device downsizes clock generator
gsdg90   10/24/2012 1:31:21 PM
NO RATINGS
MEMS oscillators are a bizarre market. It is an interesting technology that offers little value (with the exception of shock and vibe) to the customer. While MEMs does offer a solid advantage in microphones and motion-sensing, overall oscillator performance (including the new breed of piezo-actuated devices) only compete with incumbent technologies when David Copperfield math is performed. The price advantage seems completely artificial when one considers the complete picture.

psevalia
User Rank
Author
re: MEMS device downsizes clock generator
psevalia   10/23/2012 11:00:47 PM
NO RATINGS
Hi Colin - SiTime (www.sitime.com) introduced MEMS-based clock generators (with no external MEMS or quartz) in 2009 and have been shipping in volume since 2010. The three devices (SiT9103, SiT9104, SiT9105) offer single-ended, differential or a combination of single-ended and differential clocks respectively and can support many interface protocols including PCI. The single-ended frequencies go up to 220 MHz and differential frequencies go up to 800 MHz. Differential standards support LVPECL, LVDS, CML and HCSL. Please see links below for more information. http://www.sitime.com/products/clock-generators/sit9103 http://www.sitime.com/products/clock-generators/sit9104 http://www.sitime.com/products/clock-generators/sit9105 Thanks Piyush Sevalia Exec VP, Marketing, SiTime Corp.

Most Recent Comments
michigan0
 
SteveHarris0
 
realjjj
 
SteveHarris0
 
SteveHarris0
 
VicVat
 
Les_Slater
 
SSDWEM
 
witeken
Most Recent Messages
9/25/2016
4:48:30 PM
michigan0 Sang Kim First, 28nm bulk is in volume manufacturing for several years by the major semiconductor companies but not 28nm FDSOI today yet. Why not? Simply because unlike 28nm bulk the LDD(Lightly Doped Drain) to minimize hot carrier generation can't be implemented in 28nm FDSOI. Furthermore, hot carrier reliability becomes worse with scaling, That is the major reason why 28nm FDSOI is not manufacturable today and will not be. Second, how can you suppress the leakage currents from such ultra short 7nm due to the short channel effects? How thin SOI thickness is required to prevent punch-through of un-dopped 7nm FDSOI? Possibly less than 4nm. Depositing such an ultra thin film less then 4nm filum uniformly and reliably over 12" wafers at the manufacturing line is extremely difficult or not even manufacturable. If not manufacturable, the 7nm FDSOI debate is over!Third, what happens when hot carriers are generated near the drain at normal operation of 7nm FDSOI? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can't go to the substrate because of the thin BOX layer. Some holes may become trapped at the BOX layer causing Vt shift. However, the vast majority of holes drift through the the un-dopped SOI channel toward the N+Source,...

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed