Although phase-change memory (PCM) technology is claimed to show promise for next-generation storage applications, challenges remain, one of which is the impact of heat on data retention lifetime of PCM devices. While the effect is a function of the material composition, it now appears it might also be caused by elements of the device structure: in particular, the crystal electrodes. Part 1 of this article established the seeded-bridge model, which allows the novel use of elevated-temperature data-retention (ETDR) results to explore the “set” parameters of PCM devices and exposed the possible negative link between scaling and poor ETDR performance. Here in part two, we will review published ETDR results to see whether the model holds true.
The accepted way of presenting ETDR data is to plot the time to failure t in the form log t = f(1/kT), where t = to exp(E/kT), k is the Boltzmann constant, T is temperature. This presents the data as a straight line whose slope corresponds to the activation energy E. I extracted ETDR test data from published work of Samsung, S. K. Hynix and IBM [2 ,6, &7] and carefully transcribed them into figure 5. As described in Part 1, I then back extrapolated the data over several decades as a means of exploring the performance (temperature and set times) at the 100 ns scale. Note, results for IBM’s “golden composition” were not available in the normal ETDR test data form described above, so the data used for that material in figure 5 is an estimate based on other similar published results.
All three devices represent the leading edge of PCM device development both in terms of device structure and active material compositions. The exact compositions of the material are not available but they are different germanium antimony tellurium (GST) compositions, that is GST225 either antimony-rich, nitrogen-doped, or germanium-rich. Also shown, as insets in figure 1, are simplified cross section diagrams that illustrate each device structure.
Click image to enlarge.
Figure 1: The ETDR results from published works of Samsung, IBM, and SK Hynix in the normal form of time to failure t = (1/kT) when back extrapolated to a set time of 100 ns (horizontal dot-dash line) and shifted for complete crystallization (as marked) the prediction of the seeded-bridge model is set temperature and required power will increase as ETDR performance improves.
Plotting the results for the three materials and associated ETDR characteristics on the same axis serves to highlight the progress made in the ETDR performance of PCM materials, from t=10 years at 85ºC to now, with claims of more than 100 years at that temperature. If the seeded bridge model is a correct description of the elevated temperature data loss and the set processes, the back extrapolation suggests that the improved materials will extract a penalty in terms of the trade-offs that must be made among temperature, “set” time, and power. For example, in order to achieve the highest data write bandwidth (shortest “set” time) for the material with the higher crystallization temperature, it will require a higher “set” current in order to raise the internal temperature of the device to achieve that “set” time, with the result of an undesirable increase in overall power dissipation for the PCM memory chip.
I think there is an oversimplified assumption that retention activation energy is going to be a fixed, well-defined number, when it's actually going to have a distribution, reflecting random defect or nucleation sites.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.