One of the biggest challenges in analog/mixed-signal IC design is uncertainty in electrical behavior and reliability. While uncertainty can be a problem at any process node, it is particularly pronounced at the advanced nodes that will be needed to meet demands in high-growth areas like mobile computing. In conventional custom IC design flows, there is little observability into the electrical impact of physical design decisions until the layout is complete and design intent can be verified through parasitic extraction and circuit simulation. The combination of electrical uncertainty combined with increasing sensitivity of AMS designs to parasitics and layout dependent effects can result in significantly higher turn-around times and more conservative designs that sacrifice performance for reliability. To mitigate the risks associated with moving to advanced nodes, IC design teams will require EDA solutions that reduce electrical uncertainty and ensure design intent is preserved during custom design.
An ideal solution would electrically verify the performance and reliability of every single physical design decision so the layout is electrically correct by construction and optimized to meet the design intent. This article describes a new EDA methodology, called electrically-aware design, where every physical design decision regarding placement and routing can be analyzed or visualized in terms of its impact on electrical performance and reliability. While this methodology can be applied to a number of use models, this article focuses on reducing the uncertainty associated with electromigration (EM)-related reliability, an increasingly serious problem at advanced process nodes.
Design productivity and time to market are highly dependent on reducing uncertainties introduced during physical design. Uncertainty in the electrical behavior and reliability of analog/mixed-signal chips results from the sensitivity of analog devices to variability and the complex parasitic interactions among devices and interconnect. Additional uncertainty results from manufacturing and layout-dependent geometric dimensions, orientations, and the distances between adjacent devices. In addition, the ability to create identical devices is often critical to meeting electrical performance and design intent from a circuit perspective.
Design choices may be used to minimize variation and maximize performance, but understanding which choice is appropriate for a given context can be a complex undertaking. In conventional custom design methodologies, designers are forced to make physical design decisions with little or no way to immediately measure the electrical consequences of their decisions. Verification through simulation or reliability checking conventionally occurs when the physical design is complete, often requiring multiple design iterations to achieve successful silicon. The lack of electrical observability until the very end makes it harder to identify the cause of the unwanted behavior and reduces the set of potential fixes.
Electrically-aware design will provide designers and layout engineers with immediate electrical feedback as layout shapes are created, and it will do this in-design. This in-design verification will also allow the electrical intent of the designer to be fed forward to ensure that each step in physical design meets their desired electrical intent. New methodologies will be required to enable incremental extraction and electrical analysis, and to provide observability into the consequences of design decisions as each decision is made. Electrically-aware design improves productivity by reducing the number of design iterations and the overall uncertainty that leads to overly conservative designs and reduced in-silicon performance and profitability.
While this article is focused on the chip creation process, it is equally applicable to the board level creation process, also at the advanced nodes. High density designs in this arena also need electrical awareness from top to bottom. EDA vendors are starting to address this with integrated tool suites incorporating schematic, simulation, PCB and documenation all rolled into one. These tools don't go far enough yet. We routinely work at geometries on the PCB that once were reserved for silicon. We have mixed signal and have to do current density analysis as well as thermal flow analysis. SI analysis is also an integral part of PCB layout and unfortunately, very few DRC tools understand how to check for unbroken return paths, proper termination placement and unexpected radiation. Parasitics from the layout need to be extracted and moved back to the simulation environment to tighten the design so it can be adjusted prior to finalization. Gone are the days when we can just throw a design over the wall to the next step in the process. More and more, the entire vertical process belongs in the hands of a single engineer, and the tools need to support that approach. As no engineer can be expected to know and comprehend all the technologies that may appear on a board,a team is now divided horizontally, so the tools need to permit collaborative efforts. Such tools are just starting to emerge, but not all are on the band wagon. At this time, only a small percentage of project absolutely fall into this category, but as time moves on, these sorts of things will become the norm. Just think of the many tools we have for board and system design that used to be the province of silicon designers. Perhaps its time for that lag to disappear.
Although this piece is so full of "marketspeak" that I needed to translate every sentence to get the drift, the point is an excellent one. Those of us who work in the low-level, wide dynamic-range analog world called "audio" learned long ago that "auto-routing" circuit boards leads most often to disaster. Given the generally poor state of analog skill, an auto-router that embraced common-impedance coupling, magnetic loop areas, and electric field coupling could eliminate thousands of badly-designed products. In audio, most of these bad designs pass bench tests but have horrible problems when connected into real-world systems where power-line noise and significant shield currents exist. I dub many of these "sensitive" designs as "power-line primadonnas".
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.