One of the biggest challenges in analog/mixed-signal IC design is uncertainty in electrical behavior and reliability. While uncertainty can be a problem at any process node, it is particularly pronounced at the advanced nodes that will be needed to meet demands in high-growth areas like mobile computing. In conventional custom IC design flows, there is little observability into the electrical impact of physical design decisions until the layout is complete and design intent can be verified through parasitic extraction and circuit simulation. The combination of electrical uncertainty combined with increasing sensitivity of AMS designs to parasitics and layout dependent effects can result in significantly higher turn-around times and more conservative designs that sacrifice performance for reliability. To mitigate the risks associated with moving to advanced nodes, IC design teams will require EDA solutions that reduce electrical uncertainty and ensure design intent is preserved during custom design.
An ideal solution would electrically verify the performance and reliability of every single physical design decision so the layout is electrically correct by construction and optimized to meet the design intent. This article describes a new EDA methodology, called electrically-aware design, where every physical design decision regarding placement and routing can be analyzed or visualized in terms of its impact on electrical performance and reliability. While this methodology can be applied to a number of use models, this article focuses on reducing the uncertainty associated with electromigration (EM)-related reliability, an increasingly serious problem at advanced process nodes.
Design productivity and time to market are highly dependent on reducing uncertainties introduced during physical design. Uncertainty in the electrical behavior and reliability of analog/mixed-signal chips results from the sensitivity of analog devices to variability and the complex parasitic interactions among devices and interconnect. Additional uncertainty results from manufacturing and layout-dependent geometric dimensions, orientations, and the distances between adjacent devices. In addition, the ability to create identical devices is often critical to meeting electrical performance and design intent from a circuit perspective.
Design choices may be used to minimize variation and maximize performance, but understanding which choice is appropriate for a given context can be a complex undertaking. In conventional custom design methodologies, designers are forced to make physical design decisions with little or no way to immediately measure the electrical consequences of their decisions. Verification through simulation or reliability checking conventionally occurs when the physical design is complete, often requiring multiple design iterations to achieve successful silicon. The lack of electrical observability until the very end makes it harder to identify the cause of the unwanted behavior and reduces the set of potential fixes.
Electrically-aware design will provide designers and layout engineers with immediate electrical feedback as layout shapes are created, and it will do this in-design. This in-design verification will also allow the electrical intent of the designer to be fed forward to ensure that each step in physical design meets their desired electrical intent. New methodologies will be required to enable incremental extraction and electrical analysis, and to provide observability into the consequences of design decisions as each decision is made. Electrically-aware design improves productivity by reducing the number of design iterations and the overall uncertainty that leads to overly conservative designs and reduced in-silicon performance and profitability.