In ST-MRAM, data is stored as a magnetic state versus an electronic charge, providing a non-volatile memory bit that does not suffer wear-out or data retention issues associated with flash technology. According to Everspin, the EMD3D064M is functionally compatible with the industry standard Jedec specification for the DDR3 interface, which delivers up to 1600 million transfers per second per I/O, translating to memory bandwidth of up to 3.2 GBytes/second at nanosecond class latency.
Everspin uses foundry vendors for front-end production. But it does back-end processing of ST-MRAM on its 200-mm production line in Chandler, Ariz. The company says it's collaborating with industry leaders to establish 300-mm MRAM tools and additional fab capacity. Everspin is also working with design partners to ensure that the required tools and support are in place to drive the rapid adoption of ST-MRAM, including the necessary memory controllers, memory modules (DIMMs) and evaluation platforms.
EMD3D064M is offered in an industry standard WBGA package aligned with the DDR3 standard. The company said its 64Mb DDR3 ST-MRAM chip is expected to be broadly available next year. More information is available through the company's website.
I thought the read current is spin-unpolarized, sensing the resistance - while the write current is spin-polarized, setting the resistance. If that is indeed the case then read-disturb should not be a problem...
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