Editor’s note: This is part one of an ongoing series on testing memory.
Engineers have traditionally characterized floating-gate NAND flash memory using DC instruments such as source-measurement units (SMUs) after pulse generators had programmed and/or erased the memory cell. This approach requires some type of switch to apply the DC or pulse signal alternately to the device under test (DUT). Occasionally, oscilloscopes were used to verify pulse fidelity (pulse width, overshoot, pulse voltage level, rise time, fall time) at the DUT. Measuring the pulse is important because the flash memory state is quite sensitive to the pulse voltage level. The use of oscilloscopes was relatively rare, even in research, however, because the required setup for oscilloscope measurements differed from that for the pulse-source/DC-measure approach. Even when scopes were used for flash characterization, the complexity of measuring the transient current meant that voltage was the only measurement taken while pulsing.
The transition to smaller geometries and multi-bit cells has increased the need for more precise pulse source and measurement for floating-gate NAND flash development. Recently, new instrumentation options for NVM testing have been developed that make it possible to measure the current and voltage simultaneously with a single instrument while applying pulses to a memory device or material. Let’s take a closer look at testing technology for two options: phase-change memory (PCM) and ferro-electric random-access memory (FRAM).
For nearly 20 years, FG NAND flash memory technology has been the non-volatile memory (NVM) technology of choice for a broad array of consumer products from digital cameras and MP3 players to smartphones and tablet computers. Because flash cells are implemented on the foundation of MOSFET transistors, they have standard source, gate (actually, control gate or CG), drain, and bulk/substrate connections. Fowler-Nordheim current tunneling through gate oxide and hot carrier injection represent the two standard methods for storing and removing charge from the floating gate (see figure 1). These methods are degradation mechanisms of standard (non-NVM) MOSFET transistors, which are also responsible for the limited endurance of flash memory.
Click image to enlarge.
Figure 1: Diagram of flash memory structure shows the program and erase conditions for Fowler-Nordheim tunneling.
Among consumer electronics manufacturers with products that incorporate memory devices, there is growing concern that floating-gate flash memory may not be able to continue providing higher storage capacities at the ever-lower cost-per-bit requirements that drive the NVM market. Research on potential alternatives to replace floating gate flash technology includes PCM, charge trap flash, resistive memory, ferro-electric memory (FRAM), and magneto-resistive memory (MRAM), and samples of each are currently available in the market in some form. The potential of other NVM technologies, including spin-transfer torque MRAM, floating-body RAM, and various types of carbon-nanotube-based memory is also being investigated.Phase-change memory
PCM cells are made of a chalcogenide alloy, i.e., an alloy with at least one element from the VI group of the periodic table, plus one element each from the V and IV groups. These same types of materials are also widely used in the active layers of rewritable optical media such as CDs and DVDs. Through the application of heat in the form of an electrical pulse (or a laser pulse in CDs/DVDs), PCM cells can be switched rapidly from an ordered crystalline phase (with low resistance) to a disordered, amorphous phase (with much higher resistance). The switch from the crystalline to the amorphous phase and back is triggered by melting and quick cooling, or a slightly slower process known as re-crystallization. Germanium antimony tellurium (GST), with a melting temperature from 500° to 600°C, has emerged as one of the most promising materials for PCM devices.
These devices can store binary data because of the differing levels of resistivity of the crystalline and amorphous phases of these alloys. The high-resistance amorphous state represents a binary 0; the low resistance crystalline state represents a binary 1. Multiple resistive levels will permit multi-bit PCM, which has been demonstrated, allowing PCM to scale and provide lower cost-per-bit. These states are stable over time, which is important for any commercial application.
In the amorphous phase, the GST material has short-range atomic order and low free-electron density, which means higher resistivity. This is sometimes referred to as the RESET phase because it is usually formed after a RESET operation, in which the temperature of the cell is raised slightly above the melting point, and then the material is suddenly quenched to cool it. The cooling rate is critical to the formation of the amorphous state, and typical resistance can be greater than 1 MO.
If the rate is too slow, then the material will be less amorphous. For so-called “slow materials,” the cooling rate is about 30 ns; for “fast materials,” it is in the range of single nanoseconds or faster. The fall time of the pulse can be slower than the required speed; what is important is the fall rate at the top of the pulse, when the cell cools from melting point to crystallization. After reaching crystallization temperature, the crystalline order is frozen. For example, the pulse fall time may be 20 ns, but it might take 5 ns to go from TMELT
, resulting in a resistance from 1 kO to 10 kO.