a gate-level simulation environment is a very high effort task because
of naming mismatches between synthesis and simulation. Synthesis is
often performed at a different RTL interface than that used by
simulation. Since signal names are not maintained during synthesis, the
process of matching the new interface to the previous interface is a
tedious, time-consuming manual task. Moreover, after place and route,
the interface can change completely, making the task even harder.
addition, this traditional approach produces a waveform that always
requires simulation to be run from time zero. This not only results in
long simulation run times; it also makes it necessary for the design
team to locate cycles that are relevant to the power estimation task.
Given that gate transfer level (GTL) waveform files are large and
complex, manually locating the relevant cycles is very time-consuming.
of the long simulation runtimes, the considerable effort to match and
debug the naming, and the effort required to locate power-relevant
simulation cycles, many design teams perform gate-level simulation only
at the final stage of the project. This is far too late in the flow to
optimize power effectively and efficiently. Indeed, many design teams
abandon power analysis before its completion — they simply run out of