This paper describes a new methodology that automatically generates a chip design’s gate-level waveform from the RTL design environment without the need to bring up the gate-level environment. The new waveform generation methodology reduces the effort to perform gate-level power estimation from weeks to hours, using established EDA technology from Springsoft and Cambridge Silicon Radio's established power estimation flow and tools. This major reduction in effort and increase in designer productivity enables CSR to analyze power characteristics much earlier in the design flow than is practically possible using traditional, high-effort gate-level analysis. Moreover, the new methodology produces waveforms identical (or nearly identical) to those generated by gate-level simulation. Consequently, the design can be analyzed and optimized iteratively throughout the post-synthesis design flow, enabling much earlier detection and easier resolution of power issues. The paper discusses:
- Power analysis challenge
- New automated gate-level waveform methodology
- Springsoft’s Siloti™ Visibility Automation System
- Analysis results
Power analysis challenge
One approach to reducing power analysis effort is to perform it at the register transfer level (RTL). Although faster and easier than gate-level analysis, its accuracy is limited to about 20 to 25 percent because synthesis/place and route are subject to many variables. These variables include the synthesizer’s various approaches to meeting timing constraints, as well as its RTL implementation choices, for example, the use of special cells or clock tree insertion techniques. Consequently, RTL analysis is inadequate for the fine-tuning necessary to achieve the low power goals of a complex VLSI design. It is suitable for comparing the power characteristics of design revisions and tracking trends. However, it is certainly not accurate enough to sign-off the design to production, especially a design that must meet a stringent power specification.
There are several approaches to estimating power consumption accurately. One of the common approaches is to estimate it on the post-place and route netlist using full annotation generated from simulation of real scenarios on the same netlist, with or without the standard delay format (SDF). In this approach all the clock tree and all the wire capacitance are taking into account in the most accurate way. This approach necessitates bringing up the gate-level design environment.