# Accelerate time-to-market by saving ESD test time

Electrostatic discharge (ESD) qualification processes have become complex and expensive with the increased cost of ESD test time due to the industry trend toward higher package pin counts for ICs. This increasing demand for routine ESD testing of every pin can be mitigated by testing only a fraction of the pins while preserving the same data quality from the test results.

To reduce test times, increase qualification speed and preserve accuracy, an intelligent sampling method can be applied to groups of pins that share the same applications. Not only does the proposed method help accelerate time to market, it builds a bridge amongst the commonly disconnected disciplines of statistics, design and test engineering. **Test time complexities **

As a part of IC product qualification, test times and test resources have become an increasing burden during evaluation for ESD. Therefore, a new approach would not only be unprecedented, but also it could lead to a venue of new ways for obtaining critical information in an expedient manner.

For semiconductor IC designs, it is now common practice to implement identical IO pins (clones) that have the same function with the same exact ESD protection cell. The clones share the same buffers and have the same macro name to identify them. In some cases, their population can be up to 70 percent of the total pin count for the device. The benefit for test time saving is significant for these cases, especially when the IC package pin counts exceed 3000. **Statistical methods for ESD **

Statisticians and industrial engineers have long known how to estimate the sigma of a population using the range from a sample, assuming the data comes from a normal distribution [1]. The expected value of the range is proportional to the sigma (**Fig. 1**).

**Click on image to enlarge.****Figure 1: The expected value, E, used in statistics as a function of the range, R, in terms of factor d2. The d2 plot represents the number of Sigmas that fit within the distribution. For example, there are 4.082 Sigmas with 30 readings.**

The proportionality constant increases as the size of the sample increases. Using the sample range as a proxy for the population sigma is convenient and easy, forming a desirable heuristic, and is commonly used in semiconductor statistical process control analyses.

Testing the sample range is ideal if failure levels are assumed to be normally distributed. The central limit theorem says that a superposition of independent random variables tends toward normality, regardless of the distribution of the random variables contributing to the sum. The many physical variations manifested in an ESD reading may average out, leading to normally distributed ESD readings. In a recent study, the ESD readings from the identically designed pins appear to come from a normal distribution [2].

**Figure 2**shows a typical distribution.

**Click on image to enlarge.****Figure 2: Typical data taken on cloned IO pins with step voltages showing a normal distribution range R from V1 (max voltage where no pins fail) to V2 (min voltage where all pins fail). VM represents the level where 50% or more pins result in failure. LSL denotes the chosen spec level that all pins must pass for the product to be qualified.**

For a possible application of sampling, one has to accept that all of the untested pins (i.e. untested clones) would give similarly distributed readings as the selected pins. But for the method to work, such distributions have to be established relative to the desired lower specification limit (LSL). The process for ready application of sampling becomes more practical when the LSL and sampled readings are farther apart (

**Fig. 3**).

**Click on image to enlarge.****Figure 3: The distance from LSL to the mean VM represents the number of Sigmas for the distribution. The farther VM is from LSL, the lower is the required sampling number to insure that all the unmeasured cloned IOs are still above the LSL.**