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Accelerate time-to-market by saving ESD test time

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Joy at TI
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re: Accelerate time-to-market by saving ESD test time
Joy at TI   4/25/2013 6:28:50 PM
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To respond to this other comment ("In custom analog land, you might as well forget all this.."): This method may not be applicable to custom analog designs. These products typically have custom I/O cells such that the method would not work anyway (must stress a minimum of 30 identical clones). The pre-work required to validate the method, limits the practical application to only high pin count products. Thus the method was designed with a narrow applicability. However, there are already several large processor designs with several hundreds of cloned IO pins in production that can greatly benefit from this sampling method. After much more scrutiny during the last 3 months a final optional test standard to be used for products with numerous cloned IO pins has been developed. This is expected to become part of the JEDEC/ESDA Joint HBM Standard in the near future. Thank you again for your response and feedback!

Joy at TI
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re: Accelerate time-to-market by saving ESD test time
Joy at TI   4/25/2013 6:26:51 PM
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We are sorry for the delay in our response as this was brought to our attention only recently, but we appreciate your comments. Here are our specific replies to your concerns. "There are some assumptions (or ignored effects) here that bear checking. Particularly, that the I*R drops in the bussing are insignificant.." This method was developed primarily for high pin count digital products. These products often use a common general purpose I/O cell that is cloned to form I/O banks. Many of these designs have distributed power clamps in each placement of the general purpose I/O cells and they are designed to have the same effective bus resistance to the supply clamp. Effectively these cloned I/O cells are identical. Once established through design checks (mandatory) that the pins are clones in every sense of the definition, the method uses random selection of these clones (a minimum of 30) to study their variations. The distribution of the data is then used to predict the unmeasured clones. All or any variations of bus resistance and inherent process variations are automatically covered under this approach. There are enough built-in checks for the method with very conservative criteria such that a 99% confidence level is guaranteed for application of the method.

dick_freebird
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re: Accelerate time-to-market by saving ESD test time
dick_freebird   11/26/2012 4:39:05 PM
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There are some assumptions (or ignored effects) here that bear checking. Particularly, that the I*R drops in the bussing are insignificant (not true on large "low power" chips); that the same ESD clamp cell is guaranteed to be hooked up the same everywhere it's used (you can get very different results by feeding a stripe from opposite ends, vs same end in/out) and of course the sensitivity of whatever's inboard of the cell is unknown a priori. In custom analog land, you might as well forget all this. Even for a structured ASIC or standard cell library, for this approach to work requires additional design style constraint and/or per- pin characterization to prove the validity of ignoring "should be same" pins.

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