To make it easier for end users to trade out parts from different suppliers, JEDEC and the Open NAND Flash Interface Workgroup (ONFI) have joined forces to develop an interoperability standard for NAND flash devices. JESD230 will help enable the design of interoperable systems that can support asynchronous SDR, synchronous DDR, and toggle DDR NAND flash devices. What kind of flexibility does it afford manufacturers and how will it affect their processes? To find out, I had a chat about the standard with Amber Huffman, chair of the ONFI board of directors and senior principal engineer, Storage Technologies Group at Intel, and Frank Chu, principal engineer with HGST and vice-chairman of the JEDEC JC-42.4 Subcommittee for Non-Volatile Memory Devices.
Kristin Lewotsky: What are the biggest challenges in developing a NAND flash interface, and how does the standard address them?
Amber Huffman: The standard is focused on key interoperability points and does not define the entire NAND flash interface. To accomplish this goal, the standard defines the NAND packages and command set definitions.
Frank Chu: The toughest part is how to integrate two NAND interfaces shipping in existing products into a combined JEDEC standard – Toggle Mode and the ONFI standard. JESD230 was completed by focusing only on the key attributes that are necessary for backward compatibility and the new attributes and features needed for moving the common standard NAND interface forward.
K.L.: The standard appears to be highly granular—does this limit the ability of vendors to differentiate their product? Is there room to include variability and still field a compliant product?
A.H.: The standard covers a very small set of interoperability points. There is a large area of differentiation that could be employed by each NAND vendor. For example, the standard does not define detailed electrical and protocol, allowing vendors to differentiate on the speeds that may be achieved in their solutions.
F.C.: JESD230 does not limit a vendor’s abilities to differentiate its NAND device; however by following JESD230, end users can easily interchange different vendor NAND device into their end product.
K.L.: What advantages or improvements does the standard bring to vendors?
A.H.: The standard formalizes common packages and command set opcodes already in use. The advantage enjoyed is by the NAND controller vendor in having confidence that these key interoperability points will be common among NAND vendors.
F.C.: The JESD230 initiative standardizes the important NAND terms and definitions such as the NAND device signal names, the key common NAND packages, and the standard NAND commands; thus all NAND vendors’ devices follow the same JEDEC nomenclatures. The same JEDEC nomenclatures will allow much easier adoption by all end users.
K.L.: From an engineering standpoint, what are the biggest challenges in adhering to the standard?
A.H.: The standard is very straightforward to comply with for command set opcodes. For packages, the challenge is to achieve targeted speeds for a particular product in a particular package based on routing, etc.
F.C.: The JESD230 standard is very clear as how NAND devices should be. We do not see any problems for a NAND vendor to adhere this standard.
K.L.: What do engineers need to know about the standard and its application?
A.H.: The standard is very straightforward in establishing interoperability points. Engineers should be aware that the standard does not define a complete NAND interface, though, so there is a large portion of design & implementation not covered the standard.
F.C.: The JESD230 is a NAND Flash Interface Interoperability standard. The items defined in this standard can help engineers understand the “interoperability” aspect of the NAND device; however, each engineer may still need to check its vendor’s NAND device product specification for the detail timing diagrams for the specific application.
K.L.: Do devices have to be certified compliant or are vendors on the honor system?
A.H.: A certification program is not planned.
F.C.: There are no plans for JTG to offer a certification program.
For more information, or to download the standard for free, go to www.jedec.org.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.