For high speed ADCs, aligning the data clock, the frame clock and the data usually requires a phase-locked loop (PLL) in both the transmitter and receiver. This alignment becomes difficult at gigahertz speed, and the speed of the data transfer is limited mainly by the receivers. Ultimately, this 6-wire method of serial transmission is not generally done above 1GHz, limiting either the speed of an ADC or its resolution.
For a 16-bit high speed ADC, this limits the sampling frequency to 62.5Msps. To achieve higher sampling frequencies, two or four lanes per ADC channel can be used. Using two lanes, the serial data rate is halved, with even and odd bits split between two serial data stream differential pairs. Using two-lane mode, a 16-bit 125Msps ADC will have a serial output data rate of 1Gbps. The LTC2195 serial LVDS family has an additional four lane mode which allows for a much slower data transfer rate of 500Mbps using 4 differential pairs per channel, for a total of 20 lines including the differential frame and clock pairs (Figure 2). This enables interfacing to less expensive FPGAs. Today 16-bit ADCs are available with double data rate (DDR) LVDS outputs which require only 16 lines per channel. Using this option, the data rate at the output will be twice the sampling frequency. The LTC2185 dual 16-bit ADCs offers DDR CMOS outputs, which reduces the number of data lines required to just 8 lines per channel. For single ADCs like the LTC2165, it no longer makes sense to provide a serial LVDS interface, since there is no difference in the number of data lines required. DDR CMOS uses 8 parallel output lines versus two lane serial LVDS which also uses 8 lines (4 lines for data and 4 lines of data and frame). In addition, serial LVDS raises the power consumption of the device, which is a concern in portable applications.
Figure 2: Digital output configurations for the 16-bit low power ADC family
For high channel density medical applications, the LTM9011 octal 14-bit 125Msps serial LVDS ADC family offers SNR performance of 73.1dB in a compact BGA package. For optimum performance, the device integrates all necessary bypass capacitance close to the die. The LTM9011 family provides a flow-through pinout, reducing the required board area for routing data I/O lines and simplifying layout to minimize issues with digital feedback.
About the author:
Alison Steer is product marketing manager, Mixed Signal Products, at Linear Technology Corp.
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