System simulators are becoming an increasingly important part of the FPGA and ASIC verification process, particularly for system-on-chips (SoCs) with performance-critical hardware accelerators and tightly-coupled embedded software. Cycle accuracy (CA) of the peripheral hardware is often a requirement or very desirable in many cases, especially if greater simulation performance over RTL simulation can be achieved. Some examples include:
Problem: Creating C-models of custom hardware
- Detailed performance and utilization of system interconnect, based on the actual hardware implementation running with its embedded software.
- Implementation of low-level drivers and firmware, which require register maps and may rely on exact latency and flow control behavior of the peripheral.
- Software optimization, which can be particularly important for algorithm hardware accelerators, codec development, as well as in cases where hardware and software are tightly coupled and there is a critical overall performance goal in latency, throughput, etc. In such scenarios, estimates by ISS and TLM can be off by a factor of three, resulting either in wasted silicon or chips that cannot meet their required performance.
When designing custom hardware blocks in RTL, or using 3rd party RTL, the creation of a C model is often impractical due to the time and effort required. Also it requires a significant level of expertise in model coding (C++ or SystemC), model verification, and protocols, if standard interface protocols are used in the IP block. These are all obstacles in creating an effective system model that includes a custom hardware block.Automatic C-model generation
Synopsys’ Synphony Model Compiler tool can automatically create hardware-accurate C models of designs using RTL, high-level datapath models in Simulink®, or a mixture of both. The C models can be used in a variety of simulators like ModelSim/VCS, Simulink, SystemC or direct execution. Using unique transformation and modeling technology, they maintain bit and cycle accuracy at the inputs and outputs of the model while achieving high simulation speeds, especially for multi-clock (multi-rate) designs. As demonstrated in the next section, users can realize over a 100 X simulation speedup while eliminating the effort to create and maintain models of their IP.