In an ideal power reduction
world, there would be a dedicated IP block for any particular chip
function. The power management scheme could then be implemented on an IP
block basis. For instance, “switch off video streaming” is implemented
simply by switching off the associated video processing and control
However, in the real world, a given IP block may
implement several functions, so switching off the block would disable
more than the one function that should be disabled. Therefore, the team
must devise a means of switching off only part of the IP block, for
example by adding interfaces to the power-control registers or signals.
This can be problematic in the case of third-party IP, where the team
may have only black box information about its behavior. In any case, the
verification challenge now includes re-verifying the redesigned IP
block(s) as well as verifying the power management circuitry.
The effects of design-for-test circuitry
circuitry (DFT) presents an additional complication. Conventional DFT
assumes that the whole chip design operates with all functions
up-and-running in order to minimize test pattern count and test time.
That is how it operates not only on the tester, but also in field
diagnostics. With power-aware design, DFT circuitry must now mesh with
the design’s power management scheme in order to avoid excessive power
consumption and unnecessary yield loss at final test.
Power-aware design requirements
The five principal design requirements for implementing and verifying a low power scheme (see Figure 1) are:
Sufficiently accurate power estimations using representative waveforms, both pre- and post-route.
Accurate analysis and visibility of the white box behavior of third-party IP prior to its modification and reuse.
The deployment and ongoing optimization of appropriate power reduction techniques, both pre- and post-integration.
functional verification at the architectural and RTL levels, both
before and after the deployment of power optimization circuitry.
Verification of hardware functionality compliance with software control sequences.
Figure 1: Power-aware design requirements
first two requirements can be addressed using commercially-available
tools that use simulation, formal methods and behavioral indexing. But
how do we tackle the remaining three requirements?
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.