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Hynix DRAM layout, process integration adapt to change

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resistion
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re: Hynix DRAM layout, process integration adapt to change
resistion   1/25/2013 7:05:34 PM
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I was intrigued by their 31 nm active area double patterning.

AD2010
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re: Hynix DRAM layout, process integration adapt to change
AD2010   12/23/2012 1:31:18 PM
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Micron & Samsung have been using 6F2 layout since many generations. So layout is not an indication of tech-node. In the early days for logic devices for defining the tech-node gate length was the main parameter then it became metal-1 pitch and the contacted gate pitch but now the most reliable parameter is the 6T-SRAM cell area. Cell area will emerge as important criteria for DRAM too.

mifb
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re: Hynix DRAM layout, process integration adapt to change
mifb   12/21/2012 9:00:14 PM
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It doesn't make sense to call it a 3xnm node when it is in reality a 4xnm DRAM technology. The reduced cell size would not justify this naming convention, since the competitors Samsung and Micron are using 6F2 designs allready. What about the IP situation, did Hynix buy the the bWL patents out of the Qimonda bankruptcy assets?

AD2010
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re: Hynix DRAM layout, process integration adapt to change
AD2010   12/19/2012 10:05:22 PM
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Yes bWl can be extended to 2x node by changing layout to 4F2. There are some processing issues but 4F2 with bWL is possible. For increasing cell capacitance, apart from looking at new dielectrics, there are some other tricks like using amorphous layers. The industry is always looking for other memory alternatives and it will come...

Rkuchibhatla
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re: Hynix DRAM layout, process integration adapt to change
Rkuchibhatla   12/19/2012 7:41:32 PM
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Nice work and good analysis. Do you think the bWL architecture can be exended to 2x nm node? I think the cell capacitance is also an issue at 2x nm and higher density requirements may push to look for other memory alternatives beyond 2x node.

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